ADLINK Technology I-Pi SMARC User Manual page 30

I-Pi-SMARC User's Guide
5.10 SPI & ESPI
5.10.1 SPI0
Name Pin # Description
SPI0_CS0# P43 SPI0 Master Chip Select 0
SPI0_CS1# P31 SPI0 Master Chip Select 1
SPI0_CK P44 SPI0 Clock
SPI0_DIN P45 SPI0 Master input / Slave output
SPI0_DO P46 SPI0 Master output / Slave input
SPI1_CS0# P54 SPI1 Master Chip Select 0
SPI1_CS1# P55 SPI1 Master Chip Select 1
SPI1_CK P56 SPI1 Clock
SPI1_DIN P57 SPI1 Master input / Slave output
SPI1_DO P58 SPI1 Master output / Slave input
Note: SPI0 on RPI header, SPI1 on plus header. See jumper settings for SPI voltage.
Page 23
I/O I/O Power
Type Level Domain
O 1.8V Standby
CMOS
O 1.8V Standby
CMOS
O 1.8V Standby
CMOS
I 1.8V Standby
CMOS
O 1.8V Standby
CMOS
O 1.8V Standby
CMOS
O 1.8V Standby
CMOS
O 1.8V Standby
CMOS
I 1.8V Standby
CMOS
O 1.8V Standby
CMOS
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PU / PD Comments
This signal can be used to select carrier SPI as
boot device
also referred to as MISO
also referred to as MOSI
See ESPI
See ESPI
See ESPI
See ESPI
See ESPI
SGET SMARC Rev 2.1