ADLINK Technology I-Pi SMARC User Manual page 20

I-Pi-SMARC User's Guide
5.4 MIPI Camera support
5.4.1 MIPI CSI0
Name Pin Description
#
CSI0_RX0+ S11 CSI0 differential input (point to point)
CSI0_RX0- S12
CSI0_RX1+ S14
S15
CSI0_RX1-
CSI0_CK+ S8 CSI0 differential clock intput (point to
CSI0_CK- S9 point)
I2C_CAM0_DAT S7 I2C data for serial camera data
/ CSI0_TX- support link or differential data lane
I2C_CAM0_CK / S5 I2C clock for serial camera data
CSI0_TX+ support link or differential data lane
CAM0_PWR# / P108 Camera 0 Power Enable, active low
GPIO0 output.
CAM0_RST# / P110 Camera 0 reset, active low output
GPIO2
CAM_MCK S6 Master clock output
Page 13
I/O I/O Power
Type Level Domain
I LVDS D-PHY Runtime
/ I LVDS M-PHY
I LVDS D-PHY Runtime
I/O OD CMOS 1.8V Runtime
/ O LVDS M-
PHY
O OD CMOS 1.8V Runtime
/ O LVDS M-
PHY
O CMOS 1.8V Runtime
O CMOS 1.8V Runtime
O CMOS 1.8V Runtime
copyright © 2024 ADLINK Technology Inc.
PU / PD Comments
PU 2.2K MIPI-CSI 2.0 uses I2C_CAM0_DAT
MIPI-CSI 3.0 uses CSI0_TX-
PU 2.2K MIPI-CSI 2.0 uses I2C_CAM0_CK
MIPI-CSI 3.0 uses CSI0_TX+
This signal is used by both CSI0 and CSI1
SGET SMARC Rev 2.1