ADLINK Technology I-Pi SMARC User Manual page 23

I-Pi-SMARC User's Guide
5.5.2 HDA
Name Pin # Description
HDA_SYNC / S50 High Definition Audio Sample
I2S2_LRCK synchronization clock to codec
HDA_SDO / S51 High Definition Audio data out to
I2S2_SDOUT codec
HDA_SDI / S52 High Definition Audio data in from
I2S2_SDIN codec
HDA_CK / S53 High Definition Audio clock to
I2S2_CK codec
HDA_RST# / P112 High Definition Audio reset output
GPIO4 to codec, low active.
Note: HDA signals are routed to the Audio Expansion Board pin header.
Page 16
I/O I/O Power
Type Level Domain
I/O 1.8V / 1.5V Runtime
CMOS
O 1.8V / 1.5V Runtime
CMOS
I/O 1.8V / 1.5V Runtime
CMOS
O 1.8V / 1.5V Runtime
CMOS
O 1.8V / 1.5V Runtime
CMOS
copyright © 2024 ADLINK Technology Inc.
PU / PD Comments
SMARC HDA Audio signalling supports 1.5V or 1.8V.
Please check with your module vendor if 1.5V or 1.8V is
supported and use an audio codec that is capable to support the
regarding I/O voltage. This specification ignores the discrepancy
between the 1.5V and 1.8V signalling, as the chance of damage in
mismatched systems is negligible.
The SMARC HD Audio pins are shared with the I2S2 pins, which
are defined to be 1.8V only.
SGET SMARC Rev 2.1