Omron CJ - REFERENCE MANUAL 02-2010 Reference Manual page 757

Interrupt input n
Internal status
If an interrupt task is being executed and an interrupt input with a different interrupt number is
received, execution of the corresponding interrupt task is placed on hold and that interrupt cause is
recorded internally. The interrupt tasks for the recorded I/O interrupt causes are executed after
execution of the current interrupt task has been completed in order of their priority.
If you want to cancel execution of I/O interrupt tasks or input interrupt tasks that are on hold, use
CLI(691) to clear the recorded interrupt causes before the interrupt tasks are executed.
(2) Setting the Time to the First Scheduled Interrupt (N = 4 or 5)
When N is 4 or 5, the contents of C specifies the time interval to the first scheduled interrupt.
MSKS(690)
Time to first
scheduled interrupt
Note 1 The CJ1M-CPU11/21 supports only one scheduled interrupt task for scheduled interrupt 0 (interrupt task
2).
2 The time unit for the time to the first interrupt is set as the Schedule Interrupt Interval in the PLC Setup
(default: 10 ms).
(3) Clearing or Holding High-speed Counter Interrupt Causes (N = 10 or 13)
When N is 10 or 13, CLI(691) clears or retains the recorded high-speed counter interrupt cause
(either target-value or range comparison) for the built-in high-speed counter interrupt specified by
N. (CJ1M CPU Units Only)
3 CJ1M CPU Units support only high-speed counter inputs 0 and 1.
Precautions
• Scheduled interrupt tasks cannot be used for CJ2H CPU Units if synchronous unit operation is
being used. An instruction error will occur if the CLI instruction is executed with N set to 4 or 5.
Example Programming
Specifying I/O Interrupts for the CS1W-INT01 or CJ1W-INT01
When CIO 0.00 is ON in this example, CLI(691) clears or holds the recorded causes for the interrupt
inputs from Interrupt Input Unit 0.
0.00
CL1
N
S
CS/CJ/NSJ Series Instructions Reference Manual (W474)
Interrupt
input n
Internal
status
Recorded interrupt cleared
Execution of scheduled
interrupt task.
15 14 13
1 1 1
D100
0
D100
F
0: Recorded interrupt input retained
1: Recorded interrupt input cleared
Recorded interrupt retained
12 11 10 9 8 7 6 5
1 0 1 0 1 1 1 1
5 F
3. Instructions
4 3 2 1 0
1 0 0 1 0
2
721
3