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Clock Pulse
Gate
Low
Inhibits
Clock
Pulse
Low
Clock Pulse
Step
Family
Logic
U69B
STEP FAMILY
Buttons
14
1
( 1)
T
12
----
T
U70
(2)
4-Bit
9
Binary
----
(4)
Counter
8
----
11
U75
Decode
Low on at least one
of each of these pairs
of inputs causes high
reset pulse at output
of U75.
(
U71A
+16 to+12
Converter
~
+
+
To
Circuit Description-Type 576
(1)
\
(2)
(4)
(4)
Digital to
Analog
Converter
Modified
Counter
Output
+
NUMBER OF STEPS
Switch
Logic Symbols:
Positive logic, Ml L-STD 806B;
see Diagrams section for
further information.
Fig. 3-5. Block diagram of counter and reset logic.
REV. FEB 1974
3-7
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