Espressif ESP32-S2 Programming Manual page 377

Chapter 2. API Reference
SPI Master
SPI Bus Lock To realize the multiplexing of different devices from different drivers (SPI Master, SPI Flash, etc.),
an SPI bus lock is applied on each SPI bus. Drivers can attach their devices onto the bus with the arbitration of the
lock.
Each bus lock are initialized with a BG (background) service registered, all devices request to do transactions on the
bus should wait until the BG to be successfully disabled.
• For SPI1 bus, the BG is the cache, the bus lock will help to disable the cache before device operations starts,
and enable it again after device releasing the lock. No devices on SPI1 is allowed using ISR (it's meaningless
for the task to yield to other tasks when the cache is disabled).
The SPI Master driver hasn't supported SPI1 bus. Only SPI Flash driver can attach to the bus.
• For other buses, the driver may register its ISR as the BG. The bus lock will block a device task when it requests
for exclusive use of the bus, try to disable the ISR, and unblock the device task allowed to exclusively use the
bus when the ISR is successfully disabled. When the task releases the lock, the lock will also try to resume the
ISR if there are pending transactions to be done in the ISR.
SPI Transactions
An SPI bus transaction consists of five phases which can be found in the table below. Any of these phases can be
skipped.
Phase Description
Com- In this phase, a command (0-16 bit) is written to the bus by the Host.
mand
Ad- In this phase, an address (0-32 bit) is transmitted over the bus by the Host.
dress
Write Host sends data to a Device. This data follows the optional command and address phases and is indis-
tinguishable from them at the electrical level.
Dummy This phase is configurable and is used to meet the timing requirements.
Read Device sends data to its Host.
The attributes of a transaction are determined by the bus configuration structure spi_bus_config_t, de-
vice configuration structure spi_device_interface_config_t, and transaction configuration structure
spi_transaction_t.
An SPI Host can send full-duplex transactions, during which the read and write phases occur simultaneously. The
total transaction length is determined by the sum of the following members:
• spi_device_interface_config_t::command_bits
• spi_device_interface_config_t::address_bits
• spi_transaction_t::length
While the member spi_transaction_t::rxlength
buffer.
In half-duplex transactions, the read and write phases are not simultaneous (one direction at a time). The lengths of the
write and read phases are determined by length and rxlength members of the struct
respectively.
The command and address phases are optional, as not every SPI device requires a command and/or address. This is
reflected in the Device's configuration: if command_bits and/or address_bits are set to zero, no command
or address phase will occur.
The read and write phases can also be optional, as not every transaction requires both writing and reading data. If
rx_buffer is NULL and SPI_TRANS_USE_RXDATA is not set, the read phase is skipped. If tx_buffer is
NULL and SPI_TRANS_USE_TXDATA is not set, the write phase is skipped.
Espressif Systems
only determines the length of data received into the
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spi_transaction_t
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