Espressif ESP32-S2 Programming Manual page 757

Chapter 2. API Reference
While a flash operation is running, interrupts can still run on CPUs A and B. It is assumed that all interrupt code is
placed into RAM. Once the interrupt allocation API is added, a flag should be added to request the interrupt to be
disabled for the duration of a flash operations.
Once the flash operation is complete, the function on CPU A sets another flag, s_flash_op_complete, to let
the task on CPU B know that it can re-enable cache and release the CPU. Then the function on CPU A re-enables
the cache on CPU A as well and returns control to the calling code.
Additionally, all API functions are protected with a mutex (s_flash_op_mutex).
In a single core environment
inter-CPU communication can take place.
API Reference - SPI Flash
Header File
• components/spi_flash/include/esp_flash_spi_init.h
Functions
esp_err_t spi_bus_add_flash_device(esp_flash_t
Add a SPI Flash device onto the SPI bus.
The bus should be already initialized by spi_bus_initialization.
Return
• ESP_ERR_INVALID_ARG: out_chip is NULL, or some field in the config is invalid.
• ESP_ERR_NO_MEM: failed to allocate memory for the chip structures.
• ESP_OK: success.
Parameters
• out_chip: Pointer to hold the initialized chip.
• config: Configuration of the chips to initialize.
esp_err_t spi_bus_remove_flash_device(esp_flash_t
Remove a SPI Flash device from the SPI bus.
Return
• ESP_ERR_INVALID_ARG: The chip is invalid.
• ESP_OK: success.
Parameters
• chip: The flash device to remove.
Structures
struct esp_flash_spi_device_config_t
Configurations for the SPI Flash to init.
Public Members
spi_host_device_t host_id
Bus to use.
int cs_io_num
GPIO pin to output the CS signal.
esp_flash_io_mode_t
IO mode to read from the Flash.
esp_flash_speed_t speed
Speed of the Flash clock.
Espressif Systems
(CONFIG_FREERTOS_UNICORE
esp_flash_spi_device_config_t
io_mode
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enabled), you need to disable both caches, so that no
**out_chip,
*config)
*chip)
746
const
Release v4.4