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800961-C Nov.
2000
区 JALLINCKRODT
The display controller consists of an 82C455 flat panel VGA con-
troller, U11, eight 64K x 4 DRAMS,
U1-U8, and three oscillators,
X1-X3.
Display Controller
The CPU transmits information to the display controller, U11.
Flip-
flop U25 is used to delay the display controller READY line for two
MC68332 clock cycles so that the display controller can be read
correctly by the MC68332.
The display controller is responsible for
generating the 4-bit wide video data stream used to refresh the
display.
In addition, the display controller generates all the sync
and timing signals for the display and also generates the multi-
plexed row and column addresses used for both display refresh
and CPU access of display memory.
The display controller supports a total of 256 Kbytes of display
memory.
The display controller serves as a DRAM controller for
the systems display memory, U1-U8.
It handles DRAM refresh,
fetches data from display memory as required to refresh the
screen, interfaces the CPU to display memory, and supplies all
necessary DRAM control signals. The display memory is arranged
as four planes of 64 Kbytes each.
Each plane is made up of two
64K x 4 DRAMS as follows:
Plane O
U6, U8
Plane 1
U5, U7
Plane 2
U1, U3
Plane 3
U2, U4
Oscillators X1 and X3 are used for internal display controller func-
tions. Oscillator X2 is used to generate the dot clock which up-
dates the LCD pixels.
3-33
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