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CPU BOARD
800961-C Nov. 2000
区 JALLINCKRODT
The CPU board consists of the following major components, each
of which will be discussed in greater detail in the following sections:
*
Microcontroller
*
Data Communications
* Digital to Analog converter
*
Analog to Digital converter
* EEPROM
+
RAM
+
ROM
Power Up
When power is applied to the microprocessor, U4, a reset control-
ler, U8, generates a low pulse on the microprocessor RESET line.
The reset pulse must be at least 35ps to ensure a proper reset.
A diode, D19, is tied between data line DO and the RESET pin so
that DO is pulled low when RESET goes low. This configures the
port size of the CSBOOT chip select to 8 bits. This is necessary
because CSBOOT is connected to an EPROM, U10, that has an 8-
bit wide data bus.
After initial power up the system may be reset by pressing the reset
push-button, PB1.
Microprocessor Configuration and Operation
The microprocessor uses a 32.768 kHz crystal, X1 as a reference
frequency source for an on-chip phase-locked loop which gener-
ates the 16.76 MHz clock speed.
The 16 external data lines (DO-D15) are buffered by two 8-bit 3-
state non-inverting bus transceivers (U2, U3). The direction of data
flow is controlled by the unbuffered R/W line U4 pin 79.
All the chip select lines (CSBOOT-CS10), the R/W line and 17 of
the 19 external address lines (A0-A16) are also buffered by 8-bit 3-
'state non-inverting bus transceivers (U1, U5, U6, U7).
DUART Configuration and Operation
Each DUART (U13, U14) provides two fully independent full duplex
asynchronous communications channels, six input lines, and eight
outputs lines.
The following discussion will refer to DUART U14. The clock input
is supplied by buffering the X1/CLK pin of DUART U13 witha
74HG14, U9. The six input lines are connected to a dip switch,
SW1. Pull ups R7-R11 are provided so that the input is high if the
switch is open and low if the switch is closed.
Four of the eight
3-19
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