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800961-C Nov. 2000
区 rr NCKRODT
One side of the console speaker is connected to +12V the other
side is connected to the collector of transistor Q3. The base of Q3
is driven by one side of an RS-422 driver, U10. The frequency and
duration of the base drive is controlled by U22 (MC68332) using
one of the TPU channels.
A capacitor, C33, is placed across the
speaker to prevent damage from high voltage spikes.
Console CPU
Speaker Control
The Console CPU consists of the following major components,
each of which will be discussed in greater detail in the following
sections:
¢ Microcontroller
* Battery Backed RAM
+ RAM
+ ROM
Power Up
When power is applied to the microprocessor, U22, a reset control-
ler, U27 generates a low pulse on the microprocessor RESET line.
The reset pulse must be at least 35us to ensure a proper reset.
„A diode, D11, is tied between data line DO and the RESET pin so
that DO is pulled low when RESET goes low. This configures the
port size of the CSBOOT chip select to 8 bits. This is necessary
because CSBOOT is connected to an EPROM, U16 that has an 8-
bit wide data bus.
Microprocessor Configuration and Operation
The microprocessor uses a 32.768 kHz crystal, X4, as a reference
freguency source for an on-chip phase-locked loop which gener-
ates the 16.76 MHz clock speed.
The 16 external data lines (DO-D15) are buffered by two 8-bit 3-
state non-inverting bus transceivers (U18, U19). The buffered data
lines are used only by the LCD controller, U11. The LCD controlier
determines the bus transceiver direction.
Sixteen address lines (A0-A15) are also buffered by 8-bit 3-state
non-inverting bus transceivers (U20, U21) and are input to the LCD
controller.
Battery Backed RAM
The DS1386, U13, is a self-contained real time clock with 8K by 8-
bits of battery backed RAM.
It contains an embedded lithium
energy source and a quartz crystal which eliminates the need for
any external circuitry. Data contained within the 8K by 8-bit
3-31
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