Analog Devices AD7194 Manual page 8

AD7194
Circuit and Timing Diagrams
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TO
OUTPUT
PIN
50pF
Figure 2. Load Circuit for Timing Characterization
CS (I)
t
1
MSB
DOUT/RDY (O)
t
2
SCLK (I)
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
CS (I)
t
8
SCLK (I)
t
9
t
DIN (I)
MSB
I = INPUT, O = OUTPUT
Figure 4. Write Cycle Timing Diagram
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I (1.6mA WITH DV = 5V,
SINK DD
100µA WITH DV = 3V)
DD
1.6V
I (200µA WITH DV = 5V,
SOURCE DD
100µA WITH DV = 3V)
DD
t
6
t
5
LSB
t
7
t
3
t
4
t
11
10
LSB