Analog Devices AD7194 Manual page 6

8-channel, 4.8 khz, ultralow noise, 24-bit sigma-delta adc with pga
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AD7194
Parameter
2
SYSTEM CALIBRATION
Full-Scale Calibration Limit
Zero-Scale Calibration
Limit
Input Span
7
POWER REQUIREMENTS
Power Supply Voltage
AV
− AGND
DD
DV
− DGND
DD
Power Supply Currents
AI
Current
DD
DI
Current
DD
I
DD
1
Temperature range: −40°C to +105°C.
2
Specification is not production tested, but is supported by characterization data at initial product release.
3
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.
4
Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system
full-scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
5
The analog inputs are configured for differential mode.
6
REJ60 is a bit in the mode register. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous
50 Hz/60 Hz rejection.
7
Digital inputs equal to DV
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Min
Typ
−1.05 × FS
0.8 × FS
3
2.7
0.85
1
2.8
3.2
3.8
4.3
0.35
0.5
1.5
or DGND.
DD
Max
Unit
1.05 × FS
V
V
2.1 × FS
V
5.25
V
5.25
V
1.1
mA
1.35
mA
3.6
mA
3.85
mA
4.7
mA
5.3
mA
0.4
mA
0.6
mA
mA
3
μA
Rev. 0 | Page 6 of 56
1
Test Conditions/Comments
Gain = 1, buffer off
Gain = 1, buffer on
Gain = 8, buffer off
Gain = 8, buffer on
Gain = 16 to 128, buffer off
Gain = 16 to 128, buffer on
DV
= 3 V
DD
DV
= 5 V
DD
External crystal used
Power-down mode

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