Analog Devices AD7194 Manual page 33

8-channel, 4.8 khz, ultralow noise, 24-bit sigma-delta adc with pga
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Single Conversion Mode
In single conversion mode, the AD7194 is placed in power-
down mode after conversions. When a single conversion is
initiated by setting MD2 to 0, MD1 to 0, and MD0 to 1 in the
mode register, the AD7194 powers up, performs a single
conversion, and then returns to power-down mode. The on-
chip oscillator requires 200 μs, approximately, to power up.
DOUT/ RDY goes low to indicate the completion of a conver-
sion. When the data-word has been read from the data register,
CS
DIN
DOUT/RDY
SCLK
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0x08
0x280060
Figure 24. Single Conversion
DOUT/ RDY goes high. If CS is low, DOUT/ RDY remains high
until another conversion is initiated and completed. The data
register can be read several times, if required, even when
DOUT/ RDY has gone high.
If the DAT_STA bit in the mode register is set to 1, the contents
of the status register are output along with the conversion each
time that the data read is performed. The four LSBs of the status
register indicate the channel to which the conversion corresponds.
0x58
Rev. 0 | Page 33 of 56
AD7194
DATA

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