Analog Devices AD7194 Manual page 42

AD7194
The output data rate equals
f = 1/t = f
ADC SETTLE
where:
f is the output data rate.
ADC
f is the master clock (4.92 MHz nominal).
CLK
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
When the analog input is constant or a channel change occurs,
valid conversions are available at a constant output data rate.
When conversions are being performed on a single channel and
a step change occurs on the analog input, the ADC continues to
output fully settled conversions if the step change is synchronized
with the conversion process. If the step change is asynchronous,
one conversion is output from the ADC that is not completely
settled (see Figure 38).
ANALOG
INPUT
ADC
OUTPUT
Figure 38. Sinc
Table 31 provides examples of output data rates and the corres-
ponding FS values.
Table 31. Examples of Output Data Rates and the
Corresponding Settling Time (Zero Latency)
FS[9:0] Output Data Rate (Hz)
480 3.3
96 16.7
80 20
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/(3 × 1024 × FS[9:0])
CLK
FULLY
SETTLED
f
1/
ADC
3
Zero Latency Operation
Settling Time (ms)
300
60
50
3
Sinc 50 Hz/60 Hz Rejection
Figure 39 show the frequency response of the sinc
FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The
output data rate is equal to 50 Hz when zero latency is disabled
and 16.7 Hz when zero latency is enabled. The sinc
50 Hz ± 1 Hz rejection of 95 dB minimum for a stable master clock.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 25
Figure 39. Sinc
When FS[9:0] is set to 80 and the master clock equals
4.92 MHz, 60 Hz rejection is achieved (see Figure 40). The
output data rate is equal to 60 Hz when zero latency is disabled
and 20 Hz when zero latency is enabled. The sinc
rejection of 95 dB minimum at 60 Hz ± 1 Hz, assuming a stable
master clock.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
Figure 40. Sinc
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50 75 100 125
FREQUENCY (Hz)
3
Filter Response (FS[9:0] = 96)
30 60 90 120
FREQUENCY (Hz)
3
Filter Response (FS[9:0] = 80)
3
filter when
3
filter gives
150
3
filter has
150