Fast Settling Mode (Sinc Filter) - Analog Devices AD7194 Manual

AD7194
The 50 Hz/60 Hz rejection can be improved by setting the
REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and
REJ60 set to 1, the filter response shown in Figure 52 is achieved.
The output data rate is unchanged but the 50 Hz/60 Hz ± 1 Hz
rejection improves to 73 dB typically.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 25
Figure 52. Sinc
(FS[9:0] = 96, Chop Enabled, REJ60 = 1)
FAST SETTLING MODE (SINC
In fast settling mode, the settling time is close to the inverse of
the first filter notch; therefore, the user can achieve 50 Hz and/or
60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz.
The settling time is equal to 1/output data rate. Therefore, the
conversion time is constant when converting on a single channel
or when converting on several channels. There is no added
latency when switching channels.
Enable the fast settling mode using Bit AVG1 and Bit AVG0 in
the mode register. In fast settling mode, a postfilter is included
4
after the sinc filter. The postfilter averages by 2, 8, or 16,
depending on the settings of the AVG1 and AVG0 bits.
CHOP MODULATOR
Figure 53. Fast Settling Mode, Sinc
Output Data Rate and Settling Time, Sinc
With chop disabled, the output data rate is
f = f /((4 + Avg − 1)× 1024 × FS[9:0])
ADC CLK
where:
f is the output data rate.
ADC
f is the master clock (4.92 MHz nominal).
CLK
Avg is the average.
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
If AVG1 = AVG0 = 0, the fast settling mode is not enabled. In
this case, Equation 1 is not relevant.
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50 75 100 125
FREQUENCY (Hz)
3
Filter Response
4
FILTER)
ADC
3 4
SINC /SINC POST FILTER
4
Filter
4
Filter
The settling time is equal to
t = 1/f
SETTLE
Table 34 lists sample FS words and the corresponding output
data rates and settling times.
Table 34. Examples of Output Data Rates and the
Corresponding Settling Time (Fast Settling Mode, Sinc
FS[9:0]
96
30
6
5
When the analog input channel is changed, there is no
additional delay in generating valid conversions—the device
functions as a zero latency ADC.
CHANNEL
150
CONVERSIONS
When the device is converting on a single channel and a step
change occurs on the analog input, the ADC does not detect the
change and continues to output conversions. If the step change
is synchronized with the conversion, only fully settled results
are output from the ADC. However, if the step change is asyn-
chronous to the conversion process, there is one intermediate
result, which is not completely settled (see Figure 55).
ANALOG
INPUT
ADC
OUTPUT
Figure 55. Step Change on Analog Input, Sinc
The output data rate is the same for chop enabled and chop
disabled in fast settling mode. However, when chop is enabled,
the settling time equals
t = 2/f
SETTLE
Therefore, if chop is enabled, the sinc
(1)
is set to 6, and averaging by 16 is enabled. The output data rate
is equal to 42.1 Hz when the master clock equals 4.92 MHz.
Therefore, the conversion time equals 1/42.10 Hz or 23.75 ms and
the settling time is equal to 47.5 ms.
50 Hz/60 Hz Rejection, Sinc
Figure 56 shows the frequency response when FS[9:0] is set to 6
and the postfilter averages by 16. This gives an output data rate
Rev. 0 | Page 46 of 56
ADC
Output Data
Average Rate (Hz)
16 2.63
16 8.4
16 42.1
16 50.53
CHANNEL B
CHANNEL A
CH A CH A CH A CH B CH B CH B
f
1/
ADC
4
Figure 54. Fast Settling, Sinc Filter
ADC
4
filter is selected, FS[9:0]
4
Filter
4
)
Settling
Time (ms)
380
118.75
23.75
19.79
CH B CH B CH B
VALID
f
1/
ADC
4
Filter