Analog Devices AD7194 Manual page 25

Table 21. Configuration Register Bit Designations
Bit Location
CON23
CON22, CON21
CON20
CON19
CON18
CON17
CON16
CON16 to CON8
CON7
CON6
CON5
CON4
CON3
CON2 to CON0
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Bit Name Description
Chop Chop enable bit.
When the chop bit is cleared, chop is disabled. With chop disabled, higher conversion rates are allowed.
For an FS word of 96 decimal and the sinc
time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and
offset drift.
When the chop bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC
are continuously removed. However, this increases the conversion time and settling time of the ADC.
For example, when FS = 96 decimal and the sinc
enabled equals 80 ms and the settling time equals 160 ms.
0 These bits must be programmed with a Logic 0 for correct operation.
REFSEL Reference select bits. The reference source for the ADC is selected using these bits.
REFSEL
0
1
0 This bit must be programmed with a Logic 0 for correct operation.
Pseudo Pseudo differential analog inputs. When the pseudo bit is set to 1, the AD7194 is configured to have 16
pseudo differential analog inputs with AINCOM as the common negative terminal. Bits CH7 to CH4
select the positive input terminal while bits CH3 to CH0 have no effect. When the pseudo bit is set to 0,
channel selection is controlled using the CH7 to CH0 bits.
0 This bit must be programmed with a Logic 0 for correct operation.
Temp Temperature sensor select bit. When the Temp bit is set to 1, the internal temperature sensor is selected. When
the Temp bit is low, the analog input channel as determined by the Pseudo bit and the CH7 to CH0 bits is
selected. The temperature sensor does not have a unique code in bits CHD3 to CHD0 of the status register.
CH7 to CH0 Channel select bits. These bits select which channel is enabled on the AD7194 (see Table 22 to Table 24).
The conversion on each channel requires the complete settling time. The four LSBs of the status register
indicate the channel corresponding to the conversion in the data register. The four LSBs correspond to
bits CH7 to CH3, that is, the positive analog input terminal.
Burn When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When Burn = 0, the
burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and
when chop is disabled.
REFDET Enables the reference detect function. When set, the NOREF bit in the status register indicates when the
external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference
detect circuitry operates only when the ADC is active.
0 This bit must be programmed with a Logic 0 for correct operation.
BUF Enables the buffer on the analog inputs.
If BUF is set, the analog inputs are buffered, allowing the user to place source impedances on the front
end without contributing gain errors to the system. When the buffer is enabled, it requires some head-
room; therefore, the voltage on any input pin must be limited to 250 mV within the power supply rails.
If cleared, the analog inputs are unbuffered, lowering the power consumption of the device. With the
buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AV
U/B Polarity select bit.
When this bit is set, unipolar operation is selected.
When this bit is cleared, bipolar operation is selected.
G2 to G0 Gain select bits. These bits are written by the user to select the ADC input range as follows:
G2 G1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
4
filter selected, the conversion time is 20 ms and the settling
4
filter is selected, the conversion time with chop
Reference Voltage
External reference applied between REFIN1(+) and REFIN1(−).
External reference applied between the AIN3/P1/REFIN2(+) and AIN4/P0/REFIN2(−) pins.
G0 Gain
0 1
1 Reserved
0 Reserved
1 8
0 16
1 32
0 64
1 128
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ADC Input Range (5 V Reference)
±2.5 V
±312.5 mV
±156.2 mV
±78.125 mV
±39.06 mV
±19.53 mV
AD7194
.
DD