Analog Devices Lite ADSP-BF538F EZ-KIT System Manual page 31

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SDRAM registers are configured automatically through the debugger each
time the processor is reset. The values in
SDRAM bank 0 is accessed through the debugger (for example, when
viewing memory windows or loading a program). The numbers were
derived for maximum flexibility and work for a system clock frequency
between 54 MHz and 133 MHz.
Table 1-2. EZ-KIT Lite Session SDRAM Default Settings
Register Value
EBIU_SDGCTL 0x0091998D
EBIU_SDBCTL 0x00000025
EBIU_SDRRC 0x000003A0
1 54 MHz <=SCLK <= 133 MHz.
To re-write the
EBIU_SDGCTL
chip in self-refresh (see the ADSP-BF538/ADSP-BF538F Blackfin Processor
Hardware Reference). Clearing the appropriate checkbox on the Target
Options dialog box, which is accessible through the Settings pull-down
menu, disables the automatic and allows manual configuration. For more
information, see online Help.
ADSP-BF538F EZ-KIT Lite Evaluation System Manual
Using ADSP-BF538F EZ-KIT Lite
Table 1-2 are used whenever
Function
Calculated with SCLK = 133 MHz
16-bit data path
External buffering timing disabled
t = 2 cycles
SCLK
WR
t = 3 cycles
SCLK
RCD
t = 3 cycles
SCLK
RP
t = 6 cycles
SCLK
RAS
pre-fetch disabled
CAS latency = 3 cycles
SCLK
disabled
SCLK1
Bank 0 enabled
Bank 0 size = 64 MB
Bank 0 column address width = 10 bits
Calculated with = 54 MHz
SCLK
= 416 clock cycles
RDIV
register within the user code, first, place the
1
1-9