Flash Memory - Analog Devices Lite ADSP-BF538F EZ-KIT System Manual

Flash Memory

Flash Memory
1-10
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Automatic configuration of SDRAM is not optimized for any
quency. Table 1-3 shows optimized configuration for the SDRAM
registers using a 125 MHz and 133 MHz
ister needs to be modified in the user code to achieve maximum
performance.
Table 1-3. SDRAM Optimum Settings
Register SCLK = 133 MHz
(CCLK = 400 MHz)
EBIU_SDGCTL 0x0091 998D
EBIU_SDBCTL 0x0000 0025
EBIU_SDRRC 0x0000 0408
An example program is included in the EZ-KIT Lite installation directory
to demonstrate the SDRAM memory setup.
The flash memory interface of the ADSP-BF538F EZ-KIT Lite can con-
nect to an external 4 MB (2M x 16-bits) ST Micro M29W320EB device
or the 1 MB internal flash memory. The size and connections of flash
memory are controlled by the flash address range switch (
chip enable (FCE) switch (
page 2-11 and "FCE Enable Switch (SW14)" on page
The default for the switch is all positions
SW6
have access to the full 4 MB of the external flash memory. The default for
the switch is all positions
SW14
the full 4 MB of the external flash memory. Each
1 MB of flash memory. The amount of available flash memory decreases
as signals are turned
~AMS
ADSP-BF538F EZ-KIT Lite Evaluation System Manual
. Only the
SCLK
SCLK = 125 MHz
(CCLK = 500 MHz)
0x0091 998D
0x0000 0025
0x0000 03A0
). See "Flash Enable Switch (SW6)" on
SW14
, which allows the user to
ON
, which allows the user to have access to
OFF
~AMS
.
OFF
fre-
SCLK
reg-
EBIU_SDRRC
) and the flash
SW6
2-12.
signal accounts for