I/O Subsystem - HP Integrity rx8620 User's & Service Manual

Introduction
Detailed HP Integrity rx8620 Server Description
System Backplane to Cell Board Connectivity
Four sets of vertical connectors serve as the point of connection for the cell boards. In addition, two vertical
connectors per cell board carry signals from the CC on the cell board to the SBA chip on the PCI-X backplane,
or an external I/O chassis PCI-X backplane, and back through the system backplane.
System Backplane to Core I/O Card Connectivity
The core I/O card connectors are right-angle connectors that mate with the system backplane. Three
connectors per core I/O card carry one PCI bus from the system to the core I/O board and three single-ended
SCSI busses from the core I/O to the system backplane. The system backplane contains two LBA PCI bus
controllers, one per core I/O board, and six 68-pin SCSI connectors (three per core I/O board).
The LBA PCI bus controllers are placed on the system backplane to facilitate removal of the core I/O cards
when standby power is on. The partition for the core I/O card must be shut down before removing the card.
Placement of the SCSI connectors on the system backplane also permits removal of a core I/O card without
having to remove cables in the process. Hot-plug circuitry is located near the system backplane/core I/O card
mating area.
System Backplane to PCI-X Backplane Connectivity
The PCI-X backplane uses two connectors for the SBA link bus and two connectors for the high-speed data
signals and the manageability signals.
SBA link bus signals are routed through the system backplane to the cell controller on each corresponding
cell board.
The high-speed data signals are routed from the SBA chips on the PCI-X backplane to the two LBA PCI bus
controllers on the system backplane.
Clocks and Reset
The system backplane contains reset and clock circuitry that propagates through the whole system. The
system backplane central clocks drive all major chip set clocks.

I/O Subsystem

The cell board to the PCI-X board path runs from the CC to the SBA, from the SBA to the ropes, from the
ropes to the LBA, and from the LBA to the PCI slots seen in Figure 1-11. The CC on cell board 0 and cell
board 1 communicates through an SBA over the SBA link. The SBA link consists of both an inbound and an
outbound link with an effective bandwidth of approximately 1 GB/sec. The SBA converts the SBA link
protocol into "ropes." A rope is defined as a high-speed, point-to-point data bus. The SBA can support up to 16
of these high-speed bi-directional rope links for a total aggregate bandwidth of approximately 4 GB/sec. Each
LBA acts as a bus bridge, supporting either one or two ropes and capable of driving 33 MHz or 66 MHz for
PCI cards. The LBAs can also drive at 66 MHz or 133 MHz for PCI-X cards. When cell board 2 and cell board
3 are present, the cell boards attach to their own associated SBA and LBA chips on the PCI-X board in the
Server Expansion Unit.
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Chapter 1