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RAM Register Map
Note1: To be able to read this info you already need to know the device address.
Note 2: These two bits show the configuration number 0~3 that will be loaded from OTP into registers at power up. When changing these
bits through I2C you instruct the chip to load another configuration from OTP. This is useful for switching between OTP configurations
when in I2C mode. This method is also used to step through each configuration for reading back OTP contents.
Table 4. RAM Register Map
Register Address
Register Bit
Decimal
Hex
00
0x00
01
0x01
02
0x02
03
0x03
04
0x04
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7
Device preprogrammed? 0 = No , 1 = Yes
2
[6..5]
I
C Device address. 00=0xD0 / 0x68, 01=0xD2 / 0x69, 10=0xD4 / 0x6A, 11=0xD6 / 0x6B
[4..2]
Reserved
[1..0]
Load Configuration number at power up.
[7..6]
Enable REF outputs: 0x = Both REF0 and REF1 disabled (unused)
10 = REF0 enabled, REF1 disabled (unused)
11 = Both REF0 and REF1 enabled
5
Reserved
4
Behavior when REF is unused: 0 = Logic "0", 1 = High Impedance (Tri-State)
[3..2]
REF outputs Power Supply Voltage: 00=01=1.8V, 10=2.5V, 11=3.3V
[1..0]
Reserved
7
Enable OUT3: 0 = Disabled (unused) , 1 = Enabled
[6..4]
OUT3 Configuration: 000 = LPHCSL , Low Power HCSL
001 = CMOS1 , Single ended CMOS on true output pin.
011 = LVDS
100 = CMOS2 , Single ended CMOS on complementary output pin.
101 = CMOSD , Differential CMOS
111 = CMOSP , Two single ended CMOS outputs, in phase
010 and 110 are not used.
[3..2]
OUT3 Power Supply Voltage: 00=01=1.8V, 10=2.5V, 11=3.3V
[1..0]
Reserved
7
Reserved
6
Behavior when OUT3 is unused: 0 = Logic "0", 1 = High Impedance (Tri-State)
5
OUT3 LPHCSL Slew Rate Control: 0 = Slow , 1 = Fast
4
OUT3 LPHCSL Impedance Control: 0 = 85 Differential , 1 = 100 Differential
[3..0]
OUT3 LPHCSL Amplitude Control: 650mVpp at 0000 ~ 950mVpp at 1111.
7
Reserved
[6..4]
OUT3 LVDS Common Mode Control: 8uA at 000 ~ 11.5uA at 111
3
Reserved
[2..0]
OUT3 LVDS Amplitude Control: 30uA at 000 ~ 65uA at 111
9FGV100x Register Descriptions and Programming Guide User Guide
Function Explanation
(2)
4
(1)
November 18, 2016
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