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Register Descriptions
The register descriptions section describes the behavior and function of the customer-programmable non-volatile-memory registers in the
9FGV100x family of clock generators.
Table 1. 9FGV100x Family Products
Product
9FGV1001
9FGV1002
9FGV1004
For details of product operation, refer to the product datasheet.
9FGV100x Clock Generator Register Set
The device contains volatile (RAM) 8-bit registers and non-volatile 8-bit registers
Programmable (OTP) and will be pre-programmed at the factory with a custom dash-code configuration.
The device operates according to settings in the RAM registers. At power-up a pre-programmed configuration is transferred from OTP to
RAM registers. The device behavior can then be modified by reprogramming the RAM registers through I2C.
The device can start up in "I2C mode" or in "Hardware Select Mode", depending upon the status of the REF0_SEL_I2C# pin at power up.
Also see the datasheet. I2C access is only possible when the device has started up in I2C mode. Startup in I2C mode is default when no
pull-up is added to the REF0_SEL_I2C# pin. Pre-programming settings determine which of the 4 OTP banks is loaded into RAM registers
at power up in I2C mode. Using I2C commands the configuration can be changed and there are also commands to reload a configuration
from a different OTP bank.
Figure 1. Register Maps
User Configuration Table Selection
At power up, the voltage at REF0_SEL_I2C# pin 23 is latched by the device and used to select the state of the SEL0/SCL and SEL1/SDA
pins
(Table
2).
When a weak pull up (10k) is placed on REF0_SEL_I2C#, the SEL0/SCL and SEL1/SDA pins will be configured as hardware select
inputs, SEL0 and SEL1. Connecting SEL0 and SEL1 to VDDD and/or GND selects one of 4 configuration register sets, CFG0 through
CFG3, which is then loaded into the non-volatile configuration registers to configure the clock synthesizer. The CFG0 through CFG3
configurations are preprogrammed at the factory according to customer specifications and assigned a specific (dash) part number.
©2016 Integrated Device Technology, Inc.
9FGV100x Register Descriptions and
Programming Guide
Table 1
showcases the products under the 9FGV100x family.
2 Ref outputs, 4 Diff outputs with 1 Integer output divider
2 Ref outputs, 4 Diff outputs with 1 Fractional output divider
2 Ref outputs, 2 Diff outputs with individual Integer output dividers
and 2 Diff outputs with 1 Fractional output divider
Description
(Figure
1). The non-volatile registers are One-Time
1
User Guide
Package
24 pins
24 pins
24 pins
November 18, 2016
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Table of Contents
Related Manuals for Renesas 9FGV100 Series
Summary of Contents for Renesas 9FGV100 Series
- Page 1 9FGV100x Register Descriptions and Programming Guide User Guide Register Descriptions The register descriptions section describes the behavior and function of the customer-programmable non-volatile-memory registers in the 9FGV100x family of clock generators. Table 1 showcases the products under the 9FGV100x family. Table 1.
- Page 2 9FGV100x Register Descriptions and Programming Guide User Guide When a weak pull down is placed on REF0_SEL_I2C# (or when it is left floating to use internal pulldown), the pins SEL0 and SEL1 will be configured as a I C interface's SDA and SCL slave bus. Configuration register set CFG0 is commonly loaded into the non-volatile configuration registers to configure the clock synthesizer but the device can be configured to load any of the other configurations.
- Page 3 9FGV100x Register Descriptions and Programming Guide User Guide Table 3. RAM Overview Register Function Explanation Address 0x00 Device / I2C settings 0x01 REF Outputs settings 0x02 0x03 OUT3 output settings 0x04 0x05 0x06 OUT2 output settings 0x07 0x08 0x09 OUT1 output settings 0x0A 0x0B 0x0C...
- Page 4 9FGV100x Register Descriptions and Programming Guide User Guide RAM Register Map Note1: To be able to read this info you already need to know the device address. Note 2: These two bits show the configuration number 0~3 that will be loaded from OTP into registers at power up. When changing these bits through I2C you instruct the chip to load another configuration from OTP.
- Page 5 9FGV100x Register Descriptions and Programming Guide User Guide Register Address Register Bit Function Explanation Decimal 0x05 Enable OUT2: 0 = Disabled (unused) , 1 = Enabled [6..4] OUT2 Configuration: 000 = LPHCSL , Low Power HCSL 001 = CMOS1 , Single ended CMOS on true output pin. 011 = LVDS 100 = CMOS2 , Single ended CMOS on complementary output pin.
- Page 6 9FGV100x Register Descriptions and Programming Guide User Guide Register Address Register Bit Function Explanation Decimal 0x0B Enable OUT0: 0 = Disabled (unused) , 1 = Enabled [6..4] OUT0 Configuration: 000 = LPHCSL , Low Power HCSL 001 = CMOS1 , Single ended CMOS on true output pin. 011 = LVDS 100 = CMOS2 , Single ended CMOS on complementary output pin.
- Page 7 9FGV100x Register Descriptions and Programming Guide User Guide Register Address Register Bit Function Explanation Decimal 0x18 FOD Reset-B: 0 = Hold FOD in Reset Mode , 1 = Release FOD. Toggle to 0 and back to 1 to apply a reset or restart of the FOD. [6..2] Reserved FOD Integer Mode: 0 = Use fractional settings for a fractional output divider value.
- Page 8 9FGV100x Register Descriptions and Programming Guide User Guide Register Address Register Bit Function Explanation Decimal 0x25 Reserved Enable Integer Output Dividers: 0 = Disabled , 1 = Enabled Enable Crystal Frequency Doubler: 0 = Disabled , 1 = Enabled Reserved OUT3 Integer Divider Enable: 0 = Disabled , 1 = Enabled OUT2 Integer Divider Enable: 0 = Disabled , 1 = Enabled [1..0]...
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Page 9: Block Diagrams
9FGV100x Register Descriptions and Programming Guide User Guide Block Diagrams Figure 3. 9FGV1004 Block Diagram Figure 4. 9FGV1002 Block Diagram Figure 5. 9FGV1001 Block Diagram Equations × Feedback Divider (see register 0x1F) CRYSTAL 9FGV1004: F / Integer Divider 1 (see registers 0x20 and 0x22) OUT3 / Integer Divider 2 (see registers 0x21 and 0x22) OUT2... -
Page 10: Appendix 1: Fractional Output Divider Configuration
9FGV100x Register Descriptions and Programming Guide User Guide Appendix 1: Fractional Output Divider Configuration The Fractional Output Divider (FOD) is composed of an 8 bit integer portion (address 0x12) and a 16 bit fractional portion (addresses 0x13 and 0x14). FOD value P = INT(P) + FRAC(P) = F / (2 ×... -
Page 11: Appendix 2: Fractional Output Divider And Spread Spectrum
9FGV100x Register Descriptions and Programming Guide User Guide Appendix 2: Fractional Output Divider and Spread Spectrum Spread spectrum capability is contained within the Fractional-N output divider associated with OUT0 and OUT1. When applied, triangle wave modulation of any spread spectrum amount, SS%AMT up to ±2.5% center spread and -5% down spread between 30 and 63kHz may be generated, independent of the output clock frequency. - Page 12 9FGV100x Register Descriptions and Programming Guide User Guide Equations Calculate the FOD output frequency from the desired clock output frequency and the Jitter Attenuator Frequency Multiplier: FOD F / Multiplier CLOCK To calculate the spread spectrum registers, first determine the value in decimal of the FOD output divider P. The value of P needs to be offset so F / (2×P) is the bottom point of the triangle modulation wave.
- Page 13 9FGV100x Register Descriptions and Programming Guide User Guide Example 1 with Down Spread : =2500MHz, F =100MHz with -0.5% Down Spread and 31.5KHz Modulation Rate. CLOCK At 100MHz the JA Multiplier is 1 so F and the JA setting is JA[1..0] = 01 binary. CLOCK FOD value P = (1 + SS% / 100) ×...
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Page 14: Appendix 3: Crystal Load Capacitance Registers
9FGV100x Register Descriptions and Programming Guide User Guide Appendix 3: Crystal Load Capacitance Registers Registers 0x0E and 0x0F contain Crystal X1 and X2 Load capacitor settings that are used to add load capacitance to X1 and X2 (a.k.a. XIN and XOUT) respectively. Figure 7. -
Page 15: Revision History
9FGV100x Register Descriptions and Programming Guide User Guide Revision History Table 7. Revision History Revision Date Description of Change November 18, 2016 Initial release Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road 1-800-345-7015 or 408-284-8200 www.IDT.com/go/support San Jose, CA 95138 USA Fax: 408-284-2775 www.IDT.com www.IDT.com/go/sales... -
Page 16: Corporate Headquarters
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