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Register Address
Register Bit
Decimal
Hex
05
0x05
06
0x06
07
0x07
08
0x08
09
0x09
10
0x0A
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7
Enable OUT2: 0 = Disabled (unused) , 1 = Enabled
[6..4]
OUT2 Configuration: 000 = LPHCSL , Low Power HCSL
001 = CMOS1 , Single ended CMOS on true output pin.
011 = LVDS
100 = CMOS2 , Single ended CMOS on complementary output pin.
101 = CMOSD , Differential CMOS
111 = CMOSP , Two single ended CMOS outputs, in phase
010 and 110 are not used.
[3..2]
OUT2 Power Supply Voltage: 00=01=1.8V, 10=2.5V, 11=3.3V
[1..0]
Reserved
7
Reserved
6
Behavior when OUT2 is unused: 0 = Logic "0", 1 = High Impedance (Tri-State)
5
OUT2 LPHCSL Slew Rate Control: 0 = Slow , 1 = Fast
4
OUT2 LPHCSL Impedance Control: 0 = 85 Differential , 1 = 100 Differential
[3..0]
OUT2 LPHCSL Amplitude Control: 650mVpp at 0000 ~ 950mVpp at 1111.
7
Reserved
[6..4]
OUT2 LVDS Common Mode Control: 8uA at 000 ~ 11.5uA at 111
3
Reserved
[2..0]
OUT2 LVDS Amplitude Control: 30uA at 000 ~ 65uA at 111
7
Enable OUT1: 0 = Disabled (unused) , 1 = Enabled
[6..4]
OUT1 Configuration: 000 = LPHCSL , Low Power HCSL
001 = CMOS1 , Single ended CMOS on true output pin.
011 = LVDS
100 = CMOS2 , Single ended CMOS on complementary output pin.
101 = CMOSD , Differential CMOS
111 = CMOSP , Two single ended CMOS outputs, in phase
010 and 110 are not used.
[3..2]
OUT1 Power Supply Voltage: 00=01=1.8V, 10=2.5V, 11=3.3V
[1..0]
Reserved
7
Reserved
6
Behavior when OUT1 is unused: 0 = Logic "0", 1 = High Impedance (Tri-State)
5
OUT1 LPHCSL Slew Rate Control: 0 = Slow , 1 = Fast
4
OUT1 LPHCSL Impedance Control: 0 = 85 Differential , 1 = 100 Differential
[3..0]
OUT1 LPHCSL Amplitude Control: 650mVpp at 0000 ~ 950mVpp at 1111.
7
Reserved
[6..4]
OUT1 LVDS Common Mode Control: 8uA at 000 ~ 11.5uA at 111
3
Reserved
[2..0]
OUT1 LVDS Amplitude Control: 30uA at 000 ~ 65uA at 111
9FGV100x Register Descriptions and Programming Guide User Guide
Function Explanation
5
November 18, 2016
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