Renesas 9FGV100 Series User Manual page 2

When a weak pull down is placed on REF0_SEL_I2C# (or when it is left floating to use internal pulldown), the pins SEL0 and SEL1 will be
2
configured as a I C interface's SDA and SCL slave bus. Configuration register set CFG0 is commonly loaded into the non-volatile
configuration registers to configure the clock synthesizer but the device can be configured to load any of the other configurations. The
2
host system can use the I C bus to update the volatile RAM registers to change the configuration, and to read status registers.
Table 2. Power-Up Setting of Hardware Select Pin vs I
REF0_SEL_I2C# Strap
at Power Up
10k pullup
10k pulldown or
floating
2
I C Interface and Register Access
2
When powered up in I C mode, the device allows access to internal RAM registers. The default device address is 0xD0 for 8 bits or 0x68
for 7 bits. The device can be preprogrammed for addresses in the range 0xD0-D2-D4-D6 for 8 bits or 0x68-69-6A-6B for 7 bits. The
device acts as a slave device on the I
interface accepts byte-oriented block write and block read operations. Two address bytes specify the register address of the byte position
of the first register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most
significant bit first). Read and write block transfers can be stopped after any complete byte transfer. During a write operation, data will not
be moved into the registers until the STOP signal is received, at which point, all data received in the block write will be written
simultaneously in the registers.
2
For full electrical I C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 100ktypical.
2
Figure 2. I C Interface and Register Access
©2016 Integrated Device Technology, Inc.
SEL1/SDA pin SEL0/SCL pin
0
0
1
1
SDA SCL
2
C bus using one of the four I
9FGV100x Register Descriptions and Programming Guide User Guide
2
C Mode, and Default OTP Configuration Register
0 OTP bank CFG0 used to initialize RAM configuration registers
1 OTP bank CFG1 used to initialize RAM configuration registers
0 OTP bank CFG2 used to initialize RAM configuration registers
1 OTP bank CFG3 used to initialize RAM configuration registers
2
I C bus enabled to access registers
OTP bank CFG0 used to initialize RAM configuration registers
2
C addresses to allow multiple devices to be used in the system. The
2
Function
November 18, 2016