Renesas 9FGV100 Series User Manual page 12

Equations
Calculate the FOD output frequency from the desired clock output frequency and the Jitter Attenuator Frequency Multiplier:
FOD F = F
OUT CLOCK
To calculate the spread spectrum registers, first determine the value in decimal of the FOD output divider P. The value of P needs to be
offset so F / (2×P) is the bottom point of the triangle modulation wave. For Down Spread the value of P is offset with the Spread
VCO
percentage and for Center Spread the value of P is offset with half of the Spread percentage.
Down Spread:
FOD value P = INT(P) + FRAC(P) = (1 + SS% / 100) × (F
See equations 2 and 3 in
Center Spread:
FOD value P = INT(P) + FRAC(P) = (1 + SS% / 200) × (F
Please note that the SS% value is the peak-to-peak value so with +/-1.0% center spread, the SS% value is 2.0%
Consider one cycle of down spread triangular modulation; the FOD value is ramped down linearly from the P value followed by a linear
ramp back up to the value of P. The modulated value of the FOD is always smaller than or equal to the value of P.
Figure 6. Spread Step and Period
The SS modulation Period is defined as the amount of time steps it takes for the triangle to move from its lowest to its highest point. The
Period is essentially half of the modulation cycle or modulation rate. One time step is defined as one cycle of the output frequency FOUT.
The Period register setting needs to be half of the Period decimal value so essentially ¼ of the modulation cycle.
Period (decimal) = F / (2×F
OUT
Period [11..0] = DEC2HEX(ROUND2INT(Period(decimal) / 2)) (7)
Given the required Spread percentage and the Period value, we can calculate the Step size:
Step (decimal) = (SS% / 100) × P / Period (8)
Step [15..0] = DEC2HEX(ROUND2INT(2
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/ Multiplier
Appendix 1: Fractional Output Divider Configuration
) (6)
SS
24
× Step(decimal))) (9)
9FGV100x Register Descriptions and Programming Guide User Guide
/ (2 × F )) (4)
VCO OUT
for address 0x12, 0x13 and 0x14 settings.
/ (2 × FOUT)) (5)
VCO
12 November 18, 2016