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Register Address
Register Bit
Decimal
Hex
24
0x18
25
0x19
26
0x1A
27
0x1B
28
0x1C
29
0x1D
30
0x1E
31
0x1F
32
0x20
33
0x21
34
0x22
35
0x23
36
0x24
©2016 Integrated Device Technology, Inc.
7
FOD Reset-B: 0 = Hold FOD in Reset Mode , 1 = Release FOD.
Toggle to 0 and back to 1 to apply a reset or restart of the FOD.
[6..2]
Reserved
1
FOD Integer Mode: 0 = Use fractional settings for a fractional output divider value.
1 = Run output divider in Integer Mode in case the output division is an integer, for the best
performance.
0
Enable FOD: 0 = FOD is Disabled , 1 = FOD is Enabled.
[7..0]
Reserved
7
PLL, VCO Band Calibration Start. Toggle to 0 and back to 1 to trigger a calibration.
The calibration engages at the moment the bit moves from 0 to 1. The calibration finds the
optimum VCO band for the current VCO frequency.
6
Override VCO Band: 0 = Use Calibrated VCO Band , 1 = Use VCO Band value in bits [5..0].
[5..0]
VCO Band Value. See bit 6.
7
Enable VCO: 0 = VCO Disabled , 1 = VCO Enabled
6
Enable Charge Pump: 0 = CP Disabled , 1 = CP Enabled.
5
Enable PLL Bias: 0 = PLL Bias Disabled , 1 = PLL Bias Enabled
rd
4
Bypass 3
Pole in Loop Filter: 0 = Use 3
[3..0]
Reserved
[7..4]
Loop Filter R-zero value
[3..0]
Reserved
[7..0]
Reserved
[7..4]
Reserved
[3..0]
Charge Pump Current
[7..0]
PLL Feedback Divider Value.
[7..0]
Integer Divider value for OUT3, bits [7..0]
[7..0]
Integer Divider value for OUT2, bits [7..0]
[7..4]
Integer Divider value for OUT2, bits [11..8]
[3..0]
Integer Divider value for OUT3, bits [11..8]
[7..0]
Reserved
[7..3]
Reserved
2
Spread Spectrum Jitter Attenuator: 0 = Disabled , 1 = Enabled
[1..0]
SS Jitter Attenuator configuration. See
Spectrum.
9FGV100x Register Descriptions and Programming Guide User Guide
Function Explanation
rd
Pole , 1 = 3
Appendix 2: Fractional Output Divider and Spread
7
rd
Pole Bypassed
November 18, 2016
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