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4.3 Connector J1
4.3.1 Pins A1 - A100
Pin Signal
Description
A1
VCC
Main Input Voltage (8.0V-20V)
A2
VCC
Main Input Voltage (8.0V-20V)
A3
VCC
Main Input Voltage (8.0V-20V)
A4
VCC
Main Input Voltage (8.0V-20V)
A5
VCC
Main Input Voltage (8.0V-20V)
A6
VCC
Main Input Voltage (8.0V-20V)
A7
VCC
Main Input Voltage (8.0V-20V)
A8
VCC
Main Input Voltage (8.0V-20V)
A9
VCC
Main Input Voltage (8.0V-20V)
A10 GND
Power Ground
A11 BATLOW#
Battery Low
A12 PLTRST#
Platform Reset
A13 GND
Power Ground
A14 USB7-
USB 2.0 Data Pair Port 7 -
A15 USB7+
USB 2.0 Data Pair Port 7 +
A16 GND
Power Ground
A17 USB6-
USB 2.0 Data Pair Port 6 -
A18 USB6+
USB 2.0 Data Pair Port 6 +
A19 GND
Power Ground
A20 DDI1_SDA_AUX-
DDI1 SDA AUX -
A21 DDI1_SCL_AUX+
DDI1 SCL AUX+
A22 GND
Power Ground
A23 DDI1_PAIR0-
DDI1 Pair 0 -
A24 DDI1_PAIR0+
DDI1 Pair 0 +
A25 GND
Power Ground
A26 DDI1_PAIR1-
DDI1 Pair 1 -
A27 DDI1_PAIR1+
DDI1 Pair 1 +
A28 GND
Power Ground
A29 DDI1_PAIR2-
DDI1 Pair 2 -
A30 DDI1_PAIR2+
DDI1 Pair 2 +
A31 GND
Power Ground
A32 DDI1_PAIR3-
DDI1 Pair 3 -
A33 DDI1_PAIR3+
DDI1 Pair 3 +
A34 GND
Power Ground
A35 eDP_AUX-
eDP AUX -
A36 eDP_AUX+
eDP AUX +
A37 GND
Power Ground
A38 eDP_TX0-
eDP Pair 0 -
A39 eDP_TX0+
eDP Pair 0 +
A40 GND
Power Ground
A41 eDP_TX1-
eDP Pair 0 -
A42 eDP_TX1+
eDP Pair 0 +
A43 GND
Power Ground
A44 eDP_TX2-
eDP Pair 0 -
A45 eDP_TX2+
eDP Pair 0 +
A46 GND
Power Ground
A47 eDP_TX3-
eDP Pair 0 -
A48 eDP_TX3+
eDP Pair 0 +
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Type
Termination
PWR 8.0-20V —
PWR 8.0-20V —
PWR 8.0-20V —
PWR 8.0-20V —
PWR 8.0-20V —
PWR 8.0-20V —
PWR 8.0-20V —
PWR 8.0-20V —
PWR 8.0-20V —
PWR GND
—
I-3.3
PU 10k 3.3V (S5)
O-3.3
—
PWR GND
—
PD 14.25k to 24.8k in
DP-I/O
PCH
PD 14.25k to 24.8k in
DP-I/O
PCH
PWR GND
—
PD 14.25k to 24.8k in
DP-I/O
PCH
PD 14.25k to 24.8k in
DP-I/O
PCH
PWR GND
—
I/O-3.3
—
I/O-3.3
—
PWR GND
—
DP-O
—
DP-O
—
PWR GND
—
DP-O
—
DP-O
—
PWR GND
—
DP-O
—
DP-O
—
PWR GND
—
DP-O
—
DP-O
—
PWR GND
—
I/O PCIE
—
LV_DIFF
I/O PCIE
—
LV_DIFF
PWR GND
—
O LV_DIFF
—
O LV_DIFF
—
PWR GND
—
O LV_DIFF
—
O LV_DIFF
—
PWR GND
—
O LV_DIFF
—
O LV_DIFF
—
PWR GND
—
O LV_DIFF
—
O LV_DIFF
—
COMh-caAP User Guide
Comment
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assertion will
prevent wake
from S3-S5 state
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