Pin
Signal
Description
H69 RSVD
H70 GND
Power Ground
H71 CSI1_RX0-
CSI1 Pair 0 Receive -
H72 CSI1_RX0+
CSI1 Pair 0 Receive +
H73 GND
Power Ground
H74 CSI1_RX1-
CSI1 Pair 1 Receive -
H75 CSI1_RX1+
CSI1 Pair 1 Receive +
H76 GND
Power Ground
H77 CSI1_RX2-
CSI1 Pair 2 Receive -
H78 CSI1_RX2+
CSI1 Pair 2 Receive +
H79 GND
Power Ground
H80 CSI1_RX3-
CSI1 Pair 3 Receive -
H81 CSI1_RX3+
CSI1 Pair 3 Receive +
H82 GND
Power Ground
H83 CSI1_CLK-
CSI1 Clock input -
H84 CSI1_CLK+
CSI1 Clock input +
H85 GND
Power Ground
H86 CSI1_I2C_CLK
CSI-2 Mode: I2C Clock line
H87 CSI1_I2C_DAT
CSI-2 Mode: I2C Data line
H88 CSI1_MCLK
CSI Master Clock for CSI1
H89 CSI1_RST#
CSI0 Reset signal
H90 CSI1_ENA
CSI0 Enable singal
H91 GND
Power Ground
H92 PCIe_REFCLKIN0-
PCIe reference clock input 0 -
H93 PCIe_REFCLKIN0+ PCIe reference clock input 0 +
H94 GND
Power Ground
H95 PCIe_REFCLKIN1-
PCIe reference clock input 1 -
H96 PCIe_REFCLKIN1+ PCIe reference clock input 1 +
H97 GND
Power Ground
H98 ETH0-1_MDIO_CLK ETH 0-1 clock signal for Management Data I/O interface NA
H99 ETH0-1_MDIO_DAT ETH 0-1 Management Data I/O interface mode
H100 PCIe_WAKE_OUT1# PCIe wake request signal
Table 47: Connector J2 Pins H1 - H100
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Type
Termination Comment
—
—
PWR GND —
—
I-1.2
—
—
I-1.2
—
—
PWR GND —
—
I-1.2
—
—
I-1.2
—
—
PWR GND —
—
I-1.2
—
—
I-1.2
—
—
PWR GND —
—
I-1.2
—
—
I-1.2
—
—
PWR GND —
—
I-1.2
—
—
I-1.2
—
—
PWR GND —
—
O-1.8
PU
—
I/O-1.8
PU
—
O-1.8
—
—
O-1.8
—
—
O-1.8
—
—
PWR GND —
—
NA
—
—
NA
—
—
PWR GND —
—
NA
—
—
NA
—
—
PWR GND —
—
—
—
NA
—
—
NA
COMh-caAP User Guide
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