Spi; Bsy Bit May Stay High When Spi Is Disabled; Bsy Bit May Stay High At The End Of A Data Transfer In Slave Mode - ST STM32F078CB Errata Sheet

Description of device limitations
2.4

SPI

2.4.1

BSY bit may stay high when SPI is disabled

Description
The BSY flag may remain high upon disabling the SPI while operating in:
•
a master transmit mode and the TXE flag is low (data register full).
• a master receive only mode (simplex receive or half-duplex bidirectional receive phase)
and an SCK strobing edge has not occurred since the transition of the RXNE flag from
low to high.
•
slave mode and NSS signal is removed during the communication.
Workaround
When the SPI operates in:
•
a master transmit mode, disable the SPI when TXE=1 and BSY=0.
• a master receive only mode, ignore the BSY flag.
•
slave mode, do not remove the NSS signal during the communication.
2.4.2

BSY bit may stay high at the end of a data transfer in slave mode

Description
In slave mode, The BSY bit is not reliable to handle the end of data frame transaction due to
some bad synchronization between the CPU clock and external SCK clock provided by the
SPI master. Sporadically, the BSY bit is not cleared at the end of a data frame transfer. As a
consequence, it is not recommended to rely on the BSY bit before entering low-power mode
or modifying the SPI configuration (e.g. direction of the bidirectional mode).
Workaround
•
When the SPI interface is in receive mode, the end of a transaction with the master can
be detected by the corresponding RXNE event when this flag is set after the last bit of
that transaction is sampled and the received data are stored.
•
When the following sequence is used, the synchronization issue does not occur. The
BSY bit works correctly and can be used to recognize the end of any transmission
transaction (including when RXNE is not raised in bidirectional mode):
a)
b)
c)
d)
Note: The second workaround can be used only when the CPU is fast enough to disable the SPI
interface after a TXE event is detected while the data frame transfer is ongoing. It cannot be
implemented when the ratio between CPU and SPI clock is low and the data frame is
particularly short. At this specific case, the timeout can be measured from the TXE event
instead by calculating a fixed number of CPU clock cycles corresponding to the time
necessary to complete the data frame transaction.
12/21
Write the last data into data register.
Poll the TXE flag till it becomes high to make sure the data transfer has started.
Disable the SPI interface by clearing the SPE bit while the last data transfer is on
going.
Poll the BSY bit till it becomes low.
DocID026420 Rev 2
STM32F078CB/RB/VB