Alinx ZYNQUltraScale+ AXU3EGB User Manual page 7

Figure 1-1-1: The Schematic Diagram of the AXU3EGB
Through this diagram, you can see the interfaces and functions that the
AXU3EGB FPGA Development Board contains:
 ACU3EG core board
It consists of ACU3EG +4GB DDR4 （ PS） +1GB DDR4 （ PL） +8GB eMMC
FLASH + 256Mb QSPI FLASH, and there are 2 crystal oscillators to
provide the clock, a single-ended 33.3333MHz crystal oscillator for the
PS system, and a differential 200MHz crystal oscillator for the PL logic
DDR reference clock.
 M.2 Interface
1 PCIEx1 standard M.2 interface, used to connect M.2 SSD solid state
drives, with a communication speed of up to 6Gbps.
 DP Output Interface
1 standard Display Port output display interface, used for video image
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