Part 2.4: Qspi Flash - Alinx ZYNQUltraScale+ AXU3EGB User Manual

PL_DDR4_BA0
PL_DDR4_BA1
PL_DDR4_RAS_B
PL_DDR4_CAS_B
PL_DDR4_WE_B
PL_DDR4_ACT_B
PL_DDR4_CS_B
PL_DDR4_BG0
PL_DDR4_RST
PL_DDR4_CLK_N
PL_DDR4_CLK_P
PL_DDR4_CKE
PL_DDR4_OTD

Part 2.4: QSPI Flash

The FPGA core board ACU3EG is equipped with one 256MBit Quad-SPI
FLASH chip to form an 8-bit bandwidth data bus, the flash model is
MT25QU256ABA1EW9, which uses the 1.8V CMOS voltage standard. Due to
the non-volatile nature of QSPI FLASH, it can be used as a boot device for the
system to store the boot image of the system. These images mainly include
FPGA bit files, ARM application code, and other user data files. The specific
models and related parameters of QSPI FLASH are shown in Table 2-4-1.
Position
U5
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the QSPI FLASH interface. Figure
2-4-1 shows the QSPI Flash in the schematic.
www.alinx.com
IO_T1U_N12_64
IO_L5N_T0U_N9_AD14N_64
IO_T2U_N12_64
IO_L5P_T0U_N8_AD14P_64
IO_L11N_T1U_N9_GC_64
IO_L13N_T2L_N1_GC_QBC_64
IO_L6P_T0U_N10_AD6P_64
IO_L2N_T0L_N3_64
IO_L7P_T1L_N0_QBC_AD13P_64
IO_L10N_T1U_N7_QBC_AD4N_64
IO_L10P_T1U_N6_QBC_AD4P_64
IO_T3U_N12_64
IO_L19N_T3L_N1_DBC_AD9N_64
Model
MT25QU256ABA1EW9
Table 2-4-1: QSPI FLASH Specification
AXU3EGB User Manual
Capacity
256Mbit
AH6
AC7
AB5
AB7
AF6
AD4
AB6
AE8
AG9
AG5
AG6
AE4
AH4
Factory
Winbond
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