Part 3.3: Dp Interface - Alinx ZYNQUltraScale+ AXU3EGB User Manual

The pin assignment of M.2 interface ZYNQ is as follows:
Signal Name
PCIE_TX_P
PCIE _TX_N
PCIE _RX_P
PCIE _RX_N
505_PCIE_REFCLK_P
505_PCIE_REFCLK_N
PCIE_RSTn_MIO37

Part 3.3: DP Interface

The AXU3EGB development board has a standard DisplayPort output
display interface for video image display. The interface supports VESA
DisplayPort V1.2a output standard, up to 4K x 2K@30Fps output, supports
Y-only, YCbCr444, YCbCr422, YCbCr420 and RGB video formats, each color
supports 6, 8, 10, or 12 bits.
The DisplayPort data transmission channel is directly driven and output by
the BANK505 PS MGT of ZU3EG, and the LANE2 and LANE3 TX signals of
MGT are connected to the DP connector in a differential signal mode. The
DisplayPort auxiliary channel is connected to the MIO pin of the PS. The
schematic diagram of the DP output interface design is shown in Figure 3-3-1:
www.alinx.com
Pin Name
505_TX0_P
505_TX0_N
505_RX0_P
505_RX0_N
505_CLK0_P
505_CLK0_N
PS_MIO37_501
AXU3EGB User Manual
Pin Number Description
E25 PCIE Data Transmit Positive
E26 PCIE Data Transmit Negative
F27 PCIE Data Receive Positive
F28 PCIE Data Receive Negative
F23 PCIE Reference Clock Positive
F24 PCIE Reference Clock Negative
J17 PCIE Reset Signal
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