Part 3.17: Dip Switch Configuration - Alinx ZYNQUltraScale+ AXU3EGB User Manual

ZYNQ pin assignment of keys
Signal Name
PS_KEY1
PL_KEY1

Part 3.17: DIP Switch Configuration

There is a 4-digit DIP switch SW1 on the FPGA development board to
configure the startup mode of the ZYNQ system. The AXU3EGB system
development platform supports 4 startup modes. The 4 startup modes are
JTAG debug mode, QSPI FLASH, EMMC and SD2.0 card startup mode. After
ZU3EG chip is powered on, it will detect the level of (PS_MODE0~3) to
determine the startup mode. The user can select different startup modes
through the DIP switch SW1 on the expansion board. The SW1 startup mode
configuration is shown in the following table 3-17-1.
SW1
www.alinx.com
Figure 3-16-1: Rest keys connection diagram
ZYNQ Pin Name
PS_MIO26
B43_L5_N
Dial Position （1， 2， 3, 4）
ON，ON，ON，ON
AXU3EGB User Manual
ZYNQ Pin Number
L15
AF12
MODE[3:0]
0000
Description
PS KEY1 Input
PL KEY1 Input
Start mode
PS JTAG
55 / 58