Part 2.7: Led - Alinx ZYNQUltraScale+ AXU3EGB User Manual

used to drive the DDR4 controller and user logic circuits in the FPGA. The
schematic diagram of this clock source is shown in Figure 2-6-4
Clock pin assignment:

Part 2.7: LED

There is a red power indicator (PWR) and a configuration LED (DONE) on
the ACU3EG core board. When the core board is powered on, the power
indicator will light up; after the FPGA configuration program, the configuration
LED light will light up. The LED Schematic in the Core Board is shown in Figure
2-7-1:
Figure 2-7-1: LED Schematic in the Core Board
www.alinx.com
Figure 2-6-4: PL system clock source
Signal Name
PL_CLK0_P
PL_CLK0_N
AXU3EGB User Manual
Pin
AE5
AF5
25 / 58