Alinx ZYNQUltraScale+ AXU3EGB User Manual page 14

can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems
are directly connected to the memory interface of the PS BANK504. The
highest operating speed of the DDR4 SDRAM on the PL side can reach
1066MHz (data rate 2133Mbps), and a piece of DDR4 is connected to the
BANK64 interface of the FPGA. The specific configuration of DDR4 SDRAM is
shown in Table 2-3-1 below:
Bit Number
U12,U14,U15,U16
The hardware design of DDR4 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR4.
The hardware connection of DDR4 SDRAM on the PS Side is shown in
Figure 2-3-1:
Figure 2-3-1: DDR3 DRAM schematic diagram
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Chip Model
MT40A512M16LY-062E
Table 2-3-1: DDR4 SDRAM Configuration
AXU3EGB User Manual
Capacity Factory
512M x 16bit Micron
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