Part 2.3: Ddr4 Dram - Alinx ZYNQUltraScale+ AXU3EGB User Manual

 Static storage interface, support NAND, 2xQuad-SPI FLASH.
 High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0,
Sata 3.1, Display Port, 4 x Tri-mode Gigabit Ethernet
 Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,
2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO
 Power management: Supports the division of four parts of power
supply Full/Low/PL/Battery.
 Encryption algorithm: support RSA, AES and SHA.
 System monitoring: 10-bit 1Mbps AD sampling for temperature and
voltage detection.
The main parameters of the PL logic part are as follows:
 Logic Cells: 154K
 Flip-flops: 141K
 Look-up-tables (LUTs): 71K
 Block RAM: 240KB
 Clock Management Units (CMTs): 3
 18x25MACCs: 360
XCZU3EG-1SFVC784I chip speed grade is -1, industrial grade, package
is SFVC784

Part 2.3: DDR4 DRAM

The ACU3EG core board is equipped with 5 Micron (Micron) 1GB DDR4
chips, model MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on
the PS side to form a 64-bit data bus bandwidth and 4GB capacity. One DDR4
chip is mounted on the PL end, which is a 16-bit data bus width and a capacity
of 1GB. The maximum operating speed of the DDR4 SDRAM on the PS side
www.alinx.com
AXU3EGB User Manual
13 / 58