Driving The Refclk Input - Analog Devices AD9776A Manual

AD9776A/AD9778A/AD9779A

DRIVING THE REFCLK INPUT

The REFCLK input requires a low jitter differential drive signal.
The signal level can range from 400 mV p-p differential to
1.6 V p-p differential centered about a 400 mV input common-
mode voltage. Looking at the single-ended inputs, REFCLK+ or
REFCLK−, each input pin can safely swing from 200 mV p-p to
800 mV p-p about the 400 mV common-mode voltage. Although
these input levels are not directly LVDS compatible, REFCLK
can be driven by an offset ac-coupled LVDS signal, as shown in
Figure 73.
0.1µF
LVDS_P_IN
LVDS_N_IN
0.1µF
Figure 73. LVDS REFCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to REFCLK, as shown in Figure 73. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS to LVDS translator, and then ac-coupled as
described in this section. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 74.
REFCLK+
50Ω
V = 400mV
CM
50Ω
REFCLK–
TTL OR CMOS
CLK INPUT
Figure 74. TTL or CMOS REFCLK Drive Circuit
A simple bias network for generating V
It is important to use CVDD18 and CGND for the clock bias
circuit. Any noise or other signal that is coupled onto the clock
is multiplied by the DAC digital input signal and can degrade
DAC performance.
1kΩ
287Ω
Rev. B | Page 42 of 56
0.1µF
50Ω
50Ω
BAV99ZXCT
HIGH SPEED
DUAL DIODE
V
is shown in Figure 75.
CM
V = 400mV
CM
1nF
0.1µF 1nF
Figure 75. REFCLK V Generator Circuit
CM
REFCLK+
REFCLK–
= 400mV
CM
CVDD18
CGND