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Alinx AX7325 User Manual

Kintex-7fpga development board
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KINTEX-7 FPGA
Development Board
AX7325
User Manual

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  • Page 1 KINTEX-7 FPGA Development Board AX7325 User Manual...

  • Page 2: Version Record

    KINTEX-7 FPGA Development Board AX7325 User Manual Version Record Version Date Release By Description Rev 1.1 2019-04-27 Rachel Zhou First Release www.alinx.com 2 / 48 alinx...

  • Page 3: Table Of Contents

    KINTEX-7 FPGA Development Board AX7325 User Manual Table of Contents Version Record...................... 2 Part 1: FPGA Development Board Introduction..........5 Part 2: FPGA Chip....................8 Part 3:DDR3 DRAM....................10 Part 4:SODIMM memory module interface............ 15 Part 5: QSPI Flash....................20 Part 6: Clock configuration................22 Part 6.2: 200Mhz differential clock source..........
  • Page 4 KINTEX-7 FPGA Development Board AX7325 User Manual The AX7325 FPGA development board, it is the XILINX KINTEX-7 FPGA development platform. The AX7325 FPGA development platform uses XILINX's KINTEX-7 chip XC7K325 solution. The FPGA development board mounts four pieces of 512MB high-speed DDR3 SDRAM chips, and a SODIMM interface on the board is used to expand the memory strip of DDR3.

  • Page 5: Part 1: Fpga Development Board Introduction

    KINTEX-7 FPGA Development Board AX7325 User Manual Part 1: FPGA Development Board Introduction The AX7325 FPGA development board is mainly composed of KINTEX-7 main chip, 4 DDR3, 1 memory stick SODIMM interface, 1 QSPI FLASH and some peripheral interfaces. The FPGA development board uses Xilinx's KINTEX-7 series of chips, model number XC7K325TFFG900.
  • Page 6 KINTEX-7 FPGA Development Board AX7325 User Manual Figure 1-1: The Schematic Diagram of the AX7325 Through this diagram, you can see the interfaces and functions that the AX7325 FPGA Development Board contains:  Xilinx KINTEX-7 FPGA chip XC7K325TFFG900  DDR3...
  • Page 7 KINTEX-7 FPGA Development Board AX7325 User Manual single-channel communication rates up to 5Gbps.  4 SFP interfaces The four high-speed transceivers of the GTX transceiver of the FPGA are connected to the transmission and reception of four optical modules to realize four high-speed optical fiber communication interfaces. Each fiber optic data communication receives and transmits at speeds of up to 10 Gb/s.

  • Page 8: Part 2: Fpga Chip

    KINTEX-7 FPGA Development Board AX7325 User Manual modules of XILINX or ALINX (HDMI input/output module, binocular camera module, high-speed AD module etc.)  JTAG Interface A 10-pin0.1 spacing standard JTAG ports for FPGA program download and debugging. Users can debug and download FPGAs through XILINX downloader.
  • Page 9 KINTEX-7 FPGA Development Board AX7325 User Manual Figure 2-2: FPGA chip XC7K325T on board The main parameters of the FPGA chip XC7K325T are as follows Name Specific parameters Logic Cells 33,280 Slices 5,200 CLB flip-flops 41,600 1,800 Block RAM（kb） DSP48 Slices...

  • Page 10: Part 3:Ddr3 Dram

    KINTEX-7 FPGA Development Board AX7325 User Manual is the voltage of each BANK of FPGA, including BANK0, BANK12~18, BANK32~34. On the AX7325 development board, BANK12~13 is connected to the FMC connector. The default voltage of V is 2.5V, which enables IO to support LVDS interface.
  • Page 11 KINTEX-7 FPGA Development Board AX7325 User Manual The hardware design of DDR3 requires strict consideration of signal integrity. We have fully considered the matching resistor/terminal resistance, trace impedance control, and trace length control in circuit design and PCB design to ensure high-speed and stable operation of DDR3.
  • Page 12 KINTEX-7 FPGA Development Board AX7325 User Manual 4 DDR3 DRAM pin assignments: Signal Name FPGA Pin Name FPGA Pin DDR3_D0 IO_L13P_T2_MRCC_32 AD18 DDR3_D1 IO_L16N_T2_32 AB18 DDR3_D2 IO_L14P_T2_SRCC_32 AD17 DDR3_D3 IO_L17P_T2_32 AB19 DDR3_D4 IO_L14N_T2_SRCC_32 AD16 DDR3_D5 IO_L17N_T2_32 AC19 DDR3_D6 IO_L13N_T2_MRCC_32 AE18...
  • Page 13 KINTEX-7 FPGA Development Board AX7325 User Manual DDR3_D34 IO_L22P_T3_34 DDR3_D35 IO_L19P_T3_34 DDR3_D36 IO_L24N_T3_34 DDR3_D37 IO_L23N_T3_34 DDR3_D38 IO_L24P_T3_34 DDR3_D39 IO_L20N_T3_34 DDR3_D40 IO_L10P_T1_34 DDR3_D41 IO_L8N_T1_34 DDR3_D42 IO_L11P_T1_SRCC_34 DDR3_D43 IO_L8P_T1_34 DDR3_D44 IO_L12P_T1_MRCC_34 DDR3_D45 IO_L10N_T1_34 DDR3_D46 IO_L11N_T1_SRCC_34 DDR3_D47 IO_L7N_T1_34 DDR3_D48 IO_L13P_T2_MRCC_34 DDR3_D49 IO_L16N_T2_34 DDR3_D50...
  • Page 14 KINTEX-7 FPGA Development Board AX7325 User Manual DDR3_DM6 IO_L18P_T2_34 DDR3_DM7 IO_L1P_T0_34 DDR3_DQS0_P IO_L15P_T2_DQS_32 DDR3_DQS0_N IO_L15N_T2_DQS_32 DDR3_DQS1_P IO_L9P_T1_DQS_32 AJ18 DDR3_DQS1_N IO_L9N_T1_DQS_32 AK18 DDR3_DQS2_P IO_L3P_T0_DQS_32 AH16 DDR3_DQS2_N IO_L3N_T0_DQS_32 AJ16 DDR3_DQS3_P IO_L21P_T3_DQS_32 AC16 DDR3_DQS3_N IO_L21N_T3_DQS_32 AC15 DDR3_DQS4_P IO_L21P_T3_DQS_34 DDR3_DQS4_N IO_L21N_T3_DQS_34 DDR3_DQS5_P IO_L9P_T1_DQS_34 DDR3_DQS5_N...

  • Page 15: Part 4:Sodimm Memory Module Interface

    IO_L4P_T0_33 Part 4:SODIMM memory module interface The AX7325 development board has a 204PIN SODIMM memory socket that expands the board's storage and data bandwidth and supports up to 8GB of Micron SODIMM DDR3 memory. The FPGA and SODIMM DDR3 memory banks have a data width of 64 bits and a maximum operating speed of 400 MHz (data rate 800 Mbps).
  • Page 16 KINTEX-7 FPGA Development Board AX7325 User Manual Figure 4-2: SODIMM interface Connection Diagram Figure 4-3: SODIMM slot on the FPGA Board www.alinx.com 16 / 48 alinx...
  • Page 17 KINTEX-7 FPGA Development Board AX7325 User Manual SODIMM slot pin assignments: Signal Name FPGA Pin Name FPGA Pin DIMM_DDR3_D0 IO_L2P_T0_18 DIMM_DDR3_D1 IO_L5P_T0_18 DIMM_DDR3_D2 IO_L5N_T0_18 DIMM_DDR3_D3 IO_L6P_T0_18 DIMM_DDR3_D4 IO_L2N_T0_18 DIMM_DDR3_D5 IO_L1P_T0_18 DIMM_DDR3_D6 IO_L4N_T0_18 DIMM_DDR3_D7 IO_L1N_T0_18 DIMM_DDR3_D8 IO_L8N_T1_18 DIMM_DDR3_D9 IO_L8P_T1_18 DIMM_DDR3_D10 IO_L7P_T1_18...
  • Page 18 KINTEX-7 FPGA Development Board AX7325 User Manual DIMM_DDR3_D34 IO_L4P_T0_16 DIMM_DDR3_D35 IO_L5N_T0_16 DIMM_DDR3_D36 IO_L2P_T0_16 DIMM_DDR3_D37 IO_L1P_T0_16 DIMM_DDR3_D38 IO_L2N_T0_16 DIMM_DDR3_D39 IO_L6P_T0_16 DIMM_DDR3_D40 IO_L8N_T1_16 DIMM_DDR3_D41 IO_L8P_T1_16 DIMM_DDR3_D42 IO_L11N_T1_SRCC_16 DIMM_DDR3_D43 IO_L7N_T1_16 DIMM_DDR3_D44 IO_L10P_T1_16 DIMM_DDR3_D45 IO_L10N_T1_16 DIMM_DDR3_D46 IO_L7P_T1_16 DIMM_DDR3_D47 IO_L11P_T1_SRCC_16 DIMM_DDR3_D48 IO_L13P_T2_MRCC_16 DIMM_DDR3_D49 IO_L17N_T2_16 DIMM_DDR3_D50...
  • Page 19 KINTEX-7 FPGA Development Board AX7325 User Manual DIMM_DDR3_DM6 IO_L14N_T2_SRCC_16 DIMM_DDR3_DM7 IO_L24N_T3_16 DIMM_DDR3_DQS0_P IO_L3P_T0_DQS_18 DIMM_DDR3_DQS0_N IO_L3N_T0_DQS_18 DIMM_DDR3_DQS1_P IO_L9P_T1_DQS_18 DIMM_DDR3_DQS1_N IO_L9N_T1_DQS_18 DIMM_DDR3_DQS2_P IO_L15P_T2_DQS_18 DIMM_DDR3_DQS2_N IO_L15N_T2_DQS_18 DIMM_DDR3_DQS3_P IO_L21P_T3_DQS_18 DIMM_DDR3_DQS3_N IO_L21N_T3_DQS_18 DIMM_DDR3_DQS4_P IO_L3P_T0_DQS_16 DIMM_DDR3_DQS4_N IO_L3N_T0_DQS_16 DIMM_DDR3_DQS5_P IO_L9P_T1_DQS_16 DIMM_DDR3_DQS5_N IO_L9N_T1_DQS_16 DIMM_DDR3_DQS6_P IO_L15P_T2_DQS_16 DIMM_DDR3_DQS6_N IO_L15N_T2_DQS_16 DIMM_DDR3_DQS7_P...

  • Page 20: Part 5: Qspi Flash

    DIMM_DDR3_RESET IO_L18N_T2_17 Part 5: QSPI Flash The AX7325 FPGA development board is equipped with one128MBit Quad-SPI FLASH, and the model is N25Q128, which uses the 3.3V CMOS voltage standard. Due to the non-volatile nature of QSPI FLASH, it can store FPGA configuration Bin files and other user data files in use.
  • Page 21 KINTEX-7 FPGA Development Board AX7325 User Manual Figure 5-1: QSPI Flash Schematic Figure 5-2: QSPI Flash on the FPGA Board QSPI Flash pin assignments: Signal Name FPGA Pin Name FPGA Pin Number FPGA_CCLK CCLK_0 FLASH_CE_B IO_L6P_T0_FCS_B_14 FLASH_D0 IO_L1P_T0_D00_MOSI_14 FLASH_D1 IO_L1N_T0_D01_DIN_14...

  • Page 22: Part 6: Clock Configuration

    KINTEX-7 FPGA Development Board AX7325 User Manual Part 6: Clock configuration The AX7325 FPGA development board provides a 200Mhz differential active clock for the FPGA system. In addition, there is a programmable clock chip SI5338P on the board to provide a differential clock source for the FPGA logic part and the high-speed transceiver GTX part.

  • Page 23: Part 6.3: Programmable Clock Source

    KINTEX-7 FPGA Development Board AX7325 User Manual System Clock pin assignments: Signal Name FPGA Pin SYS_CLK_P AE10 SYS_CLK_N AF10 Part 6.3: Programmable clock source The programmable clock source mainly provides programmable reference clocks for the high-speed transceiver GTX and DIMM DDR controllers.
  • Page 24 KINTEX-7 FPGA Development Board AX7325 User Manual Figure 6-3: Programmable Clock Source Schematic Figure 6-4: Programmable Clock Source on the FPGA Board Programmable Clock Source FPGA pin assignments: Signal Name FPGA Pin PLL_SCL PLL_SDA www.alinx.com 24 / 48 alinx...

  • Page 25: Part7: Usb To Serial Port

    CLK3_N Part7: USB to Serial Port The AX7325 FPGA development board is equipped with a Uart to USB interface for serial communication and debugging of the development board. The conversion chip uses the USB-UAR chip of Silicon Labs CP2102GM. The CP2102 serial chip and the FPGA are connected by a level-shifting chip to adapt to different FPGA BANK voltages.

  • Page 26: Part 8: Sfp Interface

    AK26 Uart Data Output Part 8: SFP Interface The AX7325 FPGA development board has four optical interfaces. Users can purchase SFP optical modules (1.25G, 2.5Goptical modules on the market) and insert them into these four optical interfaces for optical data communication.
  • Page 27 KINTEX-7 FPGA Development Board AX7325 User Manual Figure 8-1: Optical Fiber Design Schematic Figure 8-2: SFP interfaces on the FPGA Board The 1 fiber interface FPGA pin assignment is as follows: Signal Name FPGA PIN Description SFP1_TX_P SFP1 Data Transfer (Positive) www.alinx.com...
  • Page 28 KINTEX-7 FPGA Development Board AX7325 User Manual SFP1_TX_N SFP1 Data Transfer (Negative) SFP1_RX_P SFP1 Data Receiver (Positive) SFP1_RX_P SFP1 Data Receiver (Negative) SFP1_TX_DIS SFP1 Optical Transfer Disable, active high SFP1_LOSS SFP1 Optical LOSS,High level means no light signal is received...

  • Page 29: Part 9: Qsfp+ Fiber Interface

    KINTEX-7 FPGA Development Board AX7325 User Manual Part 9: QSFP+ Fiber interface The AX7325 development board has a four-small fiber optic interface that plugs into the QSFP+. The fiber optic transceiver integrates 4 transmit channels and 4 receive channels. This 4-channel pluggable interface has a transfer rate of 40Gbps.
  • Page 30 KINTEX-7 FPGA Development Board AX7325 User Manual Figure 9-2: QSFP+ fiber communication interface on the Board The QSFP+ fiber interface FPGA pin assignments are as follows: Signal Name FPGA Pin Description QSFP1_TX_P QSFP + 1 Channel Data Transmission Positive QSFP1_TX_N...

  • Page 31: Part 10: Pcie Slot

    Supports PCI Express 2.0 standard, single channel communication rate up to 5Gbps. The design diagram of the PCIe interface of the AX7325 FPGA development board is shown in Figure 10-1, where the TX transmit signal and the reference clock CLK signal are connected in AC coupled mode.
  • Page 32 KINTEX-7 FPGA Development Board AX7325 User Manual Figure 10-1: PCIe x 8 Interface Design Diagram Figure 10-2: PCIex8 on the FPGA Board PCIex8 Interface Pin Assignment: Signal Name FPGA Pin Description PCIE_RX0_P PCIE Channel 0 Data Receive Positive PCIE_RX0_N PCIE Channel 0 Data Receive Negative...

  • Page 33: Part 11: Temperature Sensor

    Part 11: Temperature Sensor A high-precision, low-power, digital temperature sensor chip is mounted on the AX7325 FPGA development board, and the model is LM75 of ON Semiconductor. The temperature accuracy of the LM75 chip is 0.5 degrees. The sensor and FPGA are directly connected to the I2C digital interface. The FPGA reads the temperature near the current FPGA development board www.alinx.com...

  • Page 34: Part 12: Sd Card Slot

    KINTEX-7 FPGA Development Board AX7325 User Manual through the I2C interface. Figure 11-1 below shows the design of the LM75 sensor chip. Figure 11-1: LM75 Sensor Schematic Figure 11-2: LM75 Sensor on the FPGA Board LM75 Sensor Pin Assignment Pin Name...
  • Page 35 Driven by these leading manufacturers, SD cards have become the most widely used memory card in consumer digital devices. The AX7325 development board includes a Micro SD card interface to provide users with access to SD card memory for storing pictures, music or other user data files.

  • Page 36: Part 13: Fmc Connector

    SD card insertion signal Part 13: FMC connector The AX7325 development board comes with a standard FMC LPC expansion port that can be connected to various FMC modules of XILINX or ALINX (HDMI input and output modules, binocular camera modules, high-speed AD modules, etc.).
  • Page 37 KINTEX-7 FPGA Development Board AX7325 User Manual Figure 13-1：FMC Connector diagram Figure 13-2：FMC Connector on the FPGA Board FMC Connectors Pin Assignment Signal Name FPGA Pin Numer FPGA Pin Description Number FMC_CLK0_P IO_L12P_T1_MRCC_12 AD23 FMC reference 1 reference clock P...
  • Page 38 KINTEX-7 FPGA Development Board AX7325 User Manual FMC_CLK1_P IO_L13P_T2_MRCC_13 AG29 FMC reference 2 reference clock P FMC_CLK1_N IO_L13N_T2_MRCC_13 AH29 FMC reference 2 reference clock N FMC reference 0 channel data FMC_LA00_CC_P IO_L13P_T2_MRCC_12 AF22 (clock) P FMC reference 0 channel data...
  • Page 39 KINTEX-7 FPGA Development Board AX7325 User Manual FMC_LA15_P IO_L1P_T0_12 FMC reference 15 channel data P FMC_LA15_N IO_L1N_T0_12 FMC reference 15 channel data N FMC_LA16_P IO_L4P_T0_12 AA22 FMC reference 16 channel data P FMC_LA16_N IO_L4N_T0_12 AA23 FMC reference 16 channel data N...

  • Page 40: Part 14: Expansion Header

    The AX7325 FPGA development board is reserved with one 0.1inch spacing standard 40-pin expansion headers J16, which is used to connect the ALINX modules or the external circuit designed by the user. The expansion port has 40 signals, of which 1-channel 5V power supply, 2-channel3.3 V power supply,3-channle ground and 34 IOs.

  • Page 41: Part 15: Led Light

    J16 Expansion Header Pin Assignment J16 Pin Number FPGA Pin J16 Pin Number FPGA Pin +5V（Output） +3.3V（Output） +3.3V（Output） Part 15: LED Light There are five red LEDs on the AX7325 FPGA development board, one of www.alinx.com 41 / 48 alinx...
  • Page 42 (PWR),one is configure indicator,fourare usersLED lights (LED1~LED4). When the AX7325 FPGA board is powered on, the power indicator will light up; whenthe AX7325 FPGA is configured, the configuration LED will light up; 4 user LEDs (LED1~LED4) are connected to the IO of the FPGA BANK17, the user can control the lighting and extinction through the program.

  • Page 43: Part16: User Buttons

    LED4 IO_25_17 User LED4 Part16: User Buttons The AX7325 FPGA development board contains two user buttons KEY1~KEY2. The button is active low. The circuit of user button part is shown in Figure 16-1. Figure 16-1: User ButtonsSchematic Figure 16-2: User Buttons on the FPGA Board www.alinx.com...

  • Page 44: Part 17: Jtag Interface

    Figure 17-1: JTAG Interface Schematic The Figure 17-2 detailed the JTAG interface on the AX7325 FPGA development board. Users can connect the PC and JTAG interface to debug the FPGA through the USB downloader provided by us. Be careful not to hot swap when JTAG cable is plugged and unplugged.

  • Page 45: Part 18: Power Supply

    Figure 17-2: JTAG Interface on the FPGA board Part 18: Power Supply The power input voltage of the AX7325 FPGA development board is DC12V, and the external +12V power supply supplies power to the FPGA development board. The power supply DC12V is converted into 1.0V for FPGA...
  • Page 46 KINTEX-7 FPGA Development Board AX7325 User Manual Figure 18-1: Power Supply Design Diagram The functions of each power distribution are shown in the following table: Power Supply Function FPGA core voltage +1.0V FPGA Bank0,Bank14，Bank15，QSIP FLASH, Clock Crystal, +3.3V SD Card, SFP Optical Module Gigabit Ethernet, HDMI, USB +1.8V...

  • Page 47: Part19: Fan

    +3.3V, VCCIO) circuit design to ensure the normal operation of the chip. Part19: Fan Because AX7325 FPGA development board generates a lot of heat when it works normally, we add a heat sink and fan to the chip on the board to prevent the chip from overheating.

  • Page 48: Part 20: Structure Diagram

    KINTEX-7 FPGA Development Board AX7325 User Manual Figure 19-2：Fan on the FPGA Board Part 20: Structure Diagram Figure 20-1: Structure Diagram (Top View) www.alinx.com 48 / 48 alinx...

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