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20.2 Operation List
Mnemonic
Operands
MOV
r,#byte
saddr,#byte
sfr,#byte
Note 1
A,r
Note 1
r,A
A,saddr
saddr,A
A,sfr
sfr,A
A,!addr16
!addr16,A
PSW,#byte
A,PSW
PSW,A
A,[DE]
[DE],A
A,[HL]
[HL],A
A,[HL+byte]
[HL+byte],A
XCH
A,X
A,r
Note 2
A,saddr
A,sfr
A,[DE]
A,[HL]
A,[HL+byte]
Notes
1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (f
Register (PCC).
CHAPTER 20 INSTRUCTION SET
Byte
Clock
r ← byte
3
6
(saddr) ← byte
3
6
sfr ← byte
3
6
A ← r
2
4
r ← A
2
4
A ← (saddr)
2
4
(saddr) ← A
2
4
A ← sfr
2
4
sfr ← A
2
4
A ← (addr16)
3
8
(addr16) ← A
3
8
PSW ← byte
3
6
A ← PSW
2
4
PSW ← A
2
4
A ← (DE)
1
6
(DE) ← A
1
6
A ← (HL)
1
6
(HL) ← A
1
6
A ← (HL+byte)
2
6
(HL+byte) ← A
2
6
A ↔ X
1
4
A ↔ r
2
6
A ↔ (saddr)
2
6
A ↔ sfr
2
6
A ↔ (DE)
1
8
A ↔ (HL)
1
8
A ↔ (HL+byte)
2
8
User's Manual U13045EJ2V0UM00
Operation
) selected by the Processor Clock Control
CPU
Flag
Z AC CY
× × ×
× × ×
243
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