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Mnemonic
Operands
CMP
A,#byte
saddr,#byte
A,r
A,saddr
A,!addr16
A,[HL]
A,[HL+byte]
ADDW
AX,#word
SUBW
AX,#word
CMPW
AX,#word
INC
r
saddr
DEC
r
saddr
INCW
rp
DECW
rp
ROR
A,1
ROL
A,1
RORC
A,1
ROLC
A,1
SET1
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CLR1
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
SET1
CY
CLR1
CY
NOT1
CY
Remark
One instruction clock cycle is one CPU clock cycle (f
Register (PCC).
246
CHAPTER 20 INSTRUCTION SET
Byte
Clock
2
4
A – byte
3
6
(saddr) – byte
2
4
A – r
2
4
A – (saddr)
3
8
A – (addr16)
1
6
A – (HL)
2
6
A – (HL+byte)
AX,CY ← AX + word
3
6
AX,CY ← AX – word
3
6
3
6
AX – word
r ← r + 1
2
4
(saddr) ← (saddr) + 1
2
4
r ← r – 1
2
4
(saddr) ← (saddr) – 1
2
4
rp ← rp + 1
1
4
rp ← rp – 1
1
4
← A
1
2
(CY,A
7
← A
1
2
(CY,A
0
(CY ← A
1
2
, A
0
(CY ← A
1
2
, A
7
(saddr.bit) ← 1
3
6
sfr.bit ← 1
3
6
A.bit ← 1
2
4
PSW.bit ← 1
3
6
(HL).bit ← 1
2
10
(saddr.bit) ← 0
3
6
sfr.bit ← 0
3
6
A.bit ← 0
2
4
PSW.bit ← 0
3
6
(HL).bit ← 0
2
10
CY ← 1
1
2
CY ← 0
1
2
CY ← CY
1
2
User's Manual U13045EJ2V0UM00
Operation
← A
) × 1
, A
0
m–1
m
← A
) × 1
, A
7
m+1
m
← CY, A
← A
) × 1
7
m–1
m
← CY, A
← A
) × 1
0
m+1
m
) selected by the Processor Clock Control
CPU
Flag
Z AC CY
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× ×
× ×
× ×
× ×
×
×
×
×
× × ×
× × ×
1
0
×
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