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Mnemonic
Operands
SUBC
A,#byte
saddr,#byte
A,r
A,saddr
A,!addr16
A,[HL]
A,[HL+byte]
AND
A,#byte
saddr,#byte
A,r
A,saddr
A,!addr16
A,[HL]
A,[HL+byte]
OR
A,#byte
saddr,#byte
A,r
A,saddr
A,!addr16
A,[HL]
A,[HL+byte]
XOR
A,#byte
saddr,#byte
A,r
A,saddr
A,!addr16
A,[HL]
A,[HL+byte]
Remark One instruction clock cycle is one CPU clock cycle (f
Register (PCC).
CHAPTER 20 INSTRUCTION SET
Byte
Clock
A,CY ← A – byte – CY
2
4
(saddr),CY ← (saddr) – byte – CY
3
6
A,CY ← A – r – CY
2
4
A,CY ← A – (saddr) – CY
2
4
A,CY ← A – (addr16) – CY
3
8
A,CY ← A – (HL) – CY
1
6
A,CY ← A – (HL+byte) – CY
2
6
A ← A ∧ byte
2
4
(saddr) ← (saddr) ∧ byte
3
6
A ← A ∧ r
2
4
A ← A ∧ (saddr)
2
4
A ← A ∧ (addr16)
3
8
A ← A ∧ (HL)
1
6
A ← A ∧ (HL+byte)
2
6
A ← A ∨ byte
2
4
(saddr) ← (saddr) ∨ byte
3
6
A ← A ∨ r
2
4
A ← A ∨ (saddr)
2
4
A ← A ∨ (addr16)
3
8
A ← A ∨ (HL)
1
6
A ← A ∨ (HL+byte)
2
6
A ← A ∨ byte
2
4
(saddr) ← (saddr) ∨ byte
3
6
A ← A ∨ r
2
4
A ← A ∨ (saddr)
2
4
A ← A ∨ (addr16)
3
8
A ← A ∨ (HL)
1
6
A ← A ∨ (HL+byte)
2
6
User's Manual U13045EJ2V0UM00
Operation
) selected by the Processor Clock Control
CPU
Flag
Z AC CY
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
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