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CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES)
12.3 Registers Controlling 10-Bit A/D Converter
The following two registers are used to control the 10-bit A/D converter.
• A/D converter mode register 0 (ADM0)
• A/D input select register 0 (ADS0)
(1) A/D converter mode register 0 (ADM0)
ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears the ADM0 to 00H.
Symbol
<7>
6
5
ADM0
ADCS0
0
FR02 FR01 FR00
ADCS0
0
Conversion disabled
1
Conversion enabled
FR02
FR01
FR00
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
Other than above
Notes
1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least
14 µ s.
2. These bit combinations must not be used, as the A/D conversion time will fall below 14 µ s.
Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined.
2. The result of conversion after ADCS0 is cleared may be undefined (for details, refer to
12.5 (5) Timing when A/D conversion result becomes undefined).
Remark f
:
System clock oscillation frequency (ceramic/crystal oscillation)
X
f
: System clock oscillation frequency (RC oscillation)
CC
152
Figure 12-2. Format of A/D Converter Mode Register 0
4
3
2
1
0
0
A/D conversion control
A/D conversion time selection
At f
= 5.0-MHz operation
X
µ
144/f
(28.8
s)
X
µ
120/f
(24 s)
X
µ
96/f
(19.2 s)
X
µ
72/f
(14.4 s)
X
Note 2
60/f
(Setting prohibited
X
Note 2
48/f
(Setting prohibited
X
Setting prohibited
User's Manual U13045EJ2V0UM00
0
Address
After reset
0
FF80H
00H
Note 1
At f
144/f
(36 s)
CC
120/f
(30 s)
CC
96/f
(24 s)
CC
72/f
(18 s)
CC
)
60/f
(15 s)
CC
)
48/f
(Setting prohibited
CC
R/W
R/W
= 4.0-MHz operation
CC
µ
µ
µ
µ
µ
Note 2
)
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