Chapter 4. DSP (internal)
A DSP is a digital signal processing chain inside the FPGA that calculates the volume
control, filtering and limiting parameters on the selected Input Source. There are as
many DSP channels as amplifier outputs on the MAXX device. DSPs are "hardwired" to
the corresponding amplifier, e.g. DSP channel 1 supplies an amplifier that is wired to
CH1 Jack on the rear panel.
Figure 13. DSP Block Image
DSP Features
Architecture
Inputs
Level Control
Filter per channel
Filter types
High- Lowpass types
FIR Filter
Delay
CurrentLimiter
Voltagelimiter
Powerlimiter
Speakerdetection
2023-01-05 | Rev. 3.17.0
FPGA based 32-bit fixed point
16 x input matrix per channel (DANTE / AES3 / MADI)
sine, white- pink- brown-noise
Mute, Volume, Phase
32 x EQ / Highpass / Lowpass
bell, notch, highshelf, lowshelf
6 - 48dB/Oct, Bessel, Butterworth, Linkwitz/Riley, Variable Q
2048 Tabs, ASCII file import
48000 Samples / 330m / 1000ms per channel
Threshold [Ap]
2 x Threshold [Vp], Attack, Release
Threshold [W], Attack, Release
20kHz Pilot Tone generating with Volume, Threshold, Debounce
MAXX/HP²
Chapter 4. DSP (internal)
Chapter 4. DSP (internal) | 23/86
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