Hardware Management Overview - Kontron AdvancedTCA AT8001 User Manual

The PLD receives clocks from the backplane (CLK1 or CLK2) and use it as a reference to Zarlink's
ZL30410 PLL. Any one of the PLL clock outputs can be use to feed the AMCs CLK1. If a backplane
clock is lost, the circuit will automatically switch to the redundant clock. If all backplane clocks are
lost, the PLL will switch to holdover mode until a clock reaper.
Also, the clock circuit can receive a clock from an AMC CLK2 and distribute it to the backplane CLK3A
or CLK3B.
In all error cases, alarms are reported through an interrupt.
This circuit is available on AT8001 with AMC support only.The PLD is field upgradable.
Customization on this device for additionnal feature is possible. Contact Kontron's technical
support for this service. If upgrade are necessary for this device, an appropriate procedure will be
provided with the code update.

2.16 Hardware Management Overview

The main processors communicate with the Intelligent Management Controller (IPMC) using the
Keyboard Controller Style (KCS) interface. BIOS uses SMM interface. The base address of the LPC
interface for SMS is 0xCA2 and 0xCA4 for SMM operation. Besides that, the BIOS is able to
communicate with the IPMC for POST error logging purposes and fault resilient purposes.
The memory subsystem of the IPMC consists of an integrated flash memory to hold the IPMC
operation code and integrated RAM for data. The field replacement unit (FRU) inventory
information is stored in the nonvolatile memory on an EEPROM connected via a local I2C interface
to the IPMC microcontroller. It is possible to store up to 4 KBytes within the FRU inventory
information. Event generation over IPMB bus to reach the ShMc SEL ensure that 'post-mortem'
logging information is available even if the main processor becomes disabled.
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AT8001 User's Guide