Kontron AdvancedTCA AT8001 User Manual page 110

B.9 0A08H: TELCLOCK0 (TELECOM CLOCK OPTION)
Address Action
HWMODE
READ
HWMODE
0xA08
WRITE
Reset
HWMODE Enable automatic switching by hardware.
HO_LOS Switch criteria in HW mode.
When set, use PLL holdover detection as the switch criteria.
When cleared, use loss of clock (internal to PLD) as the switch criteria.
MS2/MS1 PLL Mode selection:
MS[2..1] = 00: normal operation
MS[2..1] = 01: holdover mode
MS[2..1] = 10: free-run mode
MS[2..1] = 11: reserved
REFALIGN Reference clock phase alignment. Changing this bit from 0 to 1 starts the alignement.
FCS Filter characteristic s of the PLL.
0: 12Hz filter without phase slope limitation
1: 6Hz filter with phase slope limited to 41ns per 1.326ms.
E3DS3/ These bits select the transmission clock frequency, when TXREFx_SEL[2..0]=111 in register
TelClock3.
E3DS3OC3
E3DS3OC3 = 0, E3DS3 = 1: 8.592MHz
E3DS3OC3 = 0, E3DS3 = 0: 11.184MHz
E3DS3OC3 = 1, E3DS3 = 1: 34.368MHz
E3DS3OC3 = 1, E3DS3 = 0: 44.736MHz
B.10 0A09H: TELCLOCK1 (TELECOM CLOCK OPTION)
Address Action
READ
0xA09 WRITE
Reset
SELCLK3B Select clock to send to backplane CLK3B:
0=from first AMC (AMC B1, CLKC), 1=from second AMC (AMC B2, CLKC).
SELCLK3A Select clock to send to backplane CLK3A
0=from first AMC (AMC B1, CLKC), 1=from second AMC (AMC B2, CLKC).
8K_16M This bit is valid only when the transmission clock is selected by setting TXREFx_SEL[2..0]=101 in
TelClock3 register. Setting this bit select the transmission clock frequency as 16.384 MHz, while
clearing it select 8.0kHz.
SEL_REFFRQ Select reference frequency (8k or 19.44M): 0 = 8kHz, 1=19.44MHz.
This bit controls the multiplexer that feeds clocks to the PLL.
0: PLL input clocks = CLK1A & CLK1B (8kHz per ATCA spec)
1: PLL input clocks = CLK2A & CLK2B (19.44MHz per ATCA spec)
SEL_RDNCLK Setting this bit selects the secondary redundant reference clock, while clearing it selects the
primary redundant reference clock. This bit is for a software (manual) switching.
Also known as "SEL" in Siemens code and in some part of the documentation.
D7 D6 D5
HO_LOS MS2
HO_LOS MS2
0 0 0
D7 D6 D5
RSV1 RSV0 SELCLK3B
NU NU SELCLK3B
X X 0
D4 D3
MS1 REFALIGN
MS1 REFALIGN
0 0
D4 D3 D2
SELCLK3A REFSEL 8K_16M SEL_REFFRQ SEL_RDNCLK
SELCLK3A NU 8K_16M SEL_REFFRQ SEL_RDNCLK
0 X 0
B-5
D2 D1 D0
FCS E3DS3 E3DS3OC3
FCS E3DS3 E3DS3OC3
0 0 0
D1 D0
0 0
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