Xilinx Zynq UltraScale+ RFSoC ZCU208 User Manual page 33

Table 3: Command List (cont'd)
Command
GetTDDRTSTrigDelay
SetTDDRTSTrigDelay
SetTDDRTSTrig
GetTDDRTSTrig
SetTDDRTSTrigSlot
GetTDDRTSTrigSlot
GetTDDRTSSlot
SetTDDRTSSlot
GetTDDRTSEnables
SetTDDRTSEnables
SetTDDRTSRst
SetTDDRTSRst
UG1433 (v1.2) October 27, 2021
RF Data Converter Evaluation Tool User Guide
Input Parameters
Tile Trig_Delay
Tile, Trig_Delay None
Trig None
None Trig
Trig_symbol, trig_frame None
None Trig_symbol, trig_frame
None Guard_Length, Symbol_Length, Slot_Config
Guard_Length, Symbol_Length,
None
Slot_Config
None Enables
Enables None
Reset None
None Reset
Appendix B: Command List
Output Parameters
Send Feedback
Description
Get the trigger delay
for ADC per tile. This
is the delay between
the TDD trigger (from
SetTDDRTSTrigSlot) to
the hw_trigger of the
capture memory.
Delay in AXI control
clock cycles (slow
clock), then resync to
tile clock.
Set the trigger delay
for ADC per tile. This
is the delay between
the TDD trigger (from
SetTDDRTSTrigSlot) to
the hw_trigger of the
capture memory.
Delay in AXI control
clock cycles (slow
clock), then resync to
tile clock.
Set the trigger. 0: stop
triggering the
memory
automatically via
hw_trigger. 1: enable
triggering of capture
memories.
Get the trigger. 0:
stop triggering the
memory
automatically via
hw_trigger. 1: enable
triggering of capture
memories.
Set the frame and
symbol to trigger on.
Get the frame and
symbol to trigger on.
Get configuration of
guard band, symbol
length, and slot
configuration (UL/DL).
Set configuration of
guard band, symbol
length, and slot
configuration (UL/DL).
Read the enable/
disable hw_trigger_en
on capture mem, per
tile.
Set the enable/disable
hw_trigger_en on
capture mem, per tile.
Reset the counters in
the TDD block.
Read the reset
register.
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