Xilinx Zynq UltraScale+ RFSoC ZCU208 User Manual page 14

• A set of two counters determine the number of symbols per frame and the number of frames
• The number of symbols is programmable, and the number of frames is always 10
• A map of downlink/uplink determine which TDD pins are asserted (DAC or ADC)
• A programmable guard band is possible
• Two trigger modes for the ADC: immediate or programmable
• The ADC programmable trigger can select the frame and symbol
• A programmable delay can be added on the trigger, available in each tile
The following figure shows a representation of the frame and symbol composition.
Guard Band DL/UL
Frame #1 of N Symbols
Block Diagram
The TDD control block diagram is shown in the following figure.
Arm Trigger &
Enable
Symbol
Length
Ports
The following table lists the TDD control block ports.
UG1433 (v1.2) October 27, 2021
RF Data Converter Evaluation Tool User Guide
Figure 8: Frames and Symbols Representation
Guard Band DL/UL
Frame #2 of N Symbols
Figure 9: TDD Control Block
Trigger Decoder
Terminal
Symbol Frame
Count
Counter Counter
AXI Registers
Chapter 3: Hardware Design
Guard Band DL/UL
Frame #9 of N Symbols
Cross Clock
Triggers to Capture Memories
Domain and Delay
TDD RTS Pins to ADC/DAC
Decoder
Guard Length
DL/UL Map
Send Feedback
Guard Band DL/UL
Frame #10 of N Symbols
X25676-083021
X25660-081321
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