Xilinx Zynq UltraScale+ RFSoC ZCU208 User Manual page 32

Table 3: Command List (cont'd)
Command
GetMemtype
SetLocalMemSample
SetMemtype
SetMMCM
MTS_Setup
SetMMCMFin
GetMMCMFin
GetMTS_Setup
GetMMCMReg
MMCM_Rst
LocalMemInfo
LocalMemTrigger
LocalMemAddr
WriteDataToMemory
ReadDataFromMemory
SetTDDRTSPinCtrl
GetTDDRTSPinCtrl
UG1433 (v1.2) October 27, 2021
RF Data Converter Evaluation Tool User Guide
Input Parameters
PL Data and Control Commands
Type, Tile Memtype
Type, Tile, Block, numsamples None
Type, Tile, mem_type Error code on failure
Type, Tile MMCM_Lock, Mult, Div, clkout0_div, Clk0DivFrac
Type, Enable None
Type, Tile, Fplin MMCM_Lock, Mult, Div, clkout0_div, Clk0DivFrac
Type, Tile MMCMFin
Type Type Tile_Mask
Type, Tile Lock, Mult, MultFrac, Div, Clk0Div, Clk0DivFrac, Clk1Div
Type, Tile None
Type, memBaseAddr, numTiles, numMem, memSize, numWords, mem_enable,
Type
mem_clksel
Type, clksel, numsamples, rfdc_ch None
Type, Tile, Block Type, Tile, Block, Addr_I, Addr_Q
Tile, Block, number of bytes, interleaved
None
pair
Tile, Block, number of bytes, interleaved
None
pair
Type, TDD_ModePin None
Type Type, TDD_ModePin
Appendix B: Command List
Output Parameters
Send Feedback
Description
Get selected memory
type (block RAM or
DDR).
Set the number of
samples to be
generated or
captured.
Set memory type to
DDR (0) or block RAM
(1).
Reconfigure the
MMCM according to
the tile settings, block
0 of this tile, and Fs.
Setup the clocking
scheme for multi-tile
synchronization
feature.
Reconfigure the
MMCM based on tile
settings, block 0 of
this tile, and Fplin
(user fabric clock
input).
Returns the current
MMCM frequency
input.
Get the current
clocking scheme for
all tiles (standard or
MTS).
Get the MMCM
settings.
Reset the MMCM.
Get information on
the memory.
Trigger the memory
channel according to
the mask rfdc_ch.
Get the memory
addresses associated
with the tile and
block.
In this case, the buffer
address is allocated
by Linux (CMA pool)
from PS DDR and
firmware writes the
data to the buffer by
reading data from a
socket.
In this case, the buffer
address is allocated
by Linux (CMA pool)
from PL DDR and
firmware reads the
data from the buffer
and sends it to a
socket. In this
command, the
number of bytes
should be aligned to
32.
Set the channel to
control, LSB channel
0, MSB channel 15.
Get the channel to
control, LSB channel
0, MSB channel 15.
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