Xilinx Zynq UltraScale+ RFSoC ZCU208 User Manual page 15

Table 1: Ports
Port Name
S00_AXI
DACx_CLK
ADCx_CLK
DACxx_tdd_mode
ADCxx_tdd_mode
Hw_trigger_en_x
Trigger_x
Trigger_ext
Register Map
The TDD control block register map is listed in the following table.
Table 2: Register Map
Address
0x0
0x4
0x8
0xC
0x10
0x14
0x18
0x30
0x34
0x38
0x3C
0x44
0x48
0x4C
0x50
Example Usage
The software commands are documented in
entered into the Command log window of the RF Evaluation tool GUI (RF Data Converter Interface
User Guide (UG1309). The following examples show the command sequences for DAC and ADC,
respectively.
UG1433 (v1.2) October 27, 2021
RF Data Converter Evaluation Tool User Guide
I/O Clock
AXI port S00_AXI_ACLK
In
In
Out S00_AXI_ACLK
Out S00_AXI_ACLK
Out ADC AXI4-Stream clock
Out ADC AXI4-Stream clock
Out Dac0_clk
DAC TDD mode pin, bit n: DAC channel n
ADC TDD mode pin, bit n: ADC channel n
Bit 0: reset, others: reserved
Bit 0 to 3: ADC hw_trigger_en control
Symbol to trigger on
Frame to trigger on
Arm the trigger
Tile 0 trigger delay
Tile 1 trigger delay
Tile 2 trigger delay
Tile 3 trigger delay
Slot length (unused)
Guard band length
Symbol length
Symbol type
Appendix B: Command
Chapter 3: Hardware Design
Description
AXI control port
DAC AXI4-Stream clock
ADC AXI4-Stream clock
Connect to DACxx TDD mode pin
Connect to ADCxx TDD mode pin
Enable external trigger on capture block
External trigger
External trigger for DAC
Description
List. The commands can be
Send Feedback
www.xilinx.com
15