Xilinx Zynq UltraScale+ RFSoC ZCU208 User Manual page 11

block is created. This block generates a TLAST pulse so that the DMA generates an interrupt
after the correct number of samples. Because the dual RF-ADC tiles have two AXI4-Stream
outputs in I/Q mode, an AXI4-Stream combiner is used to write both streams in the DDR
memory. Consequently, the real mode cannot be used to capture the dual RF-ADC tiles in the
DDR. The RF-ADC DDR block architecture is shown in the following figures.
Figure 4: RF-ADC DDR Block Architecture for Quad RF-ADC Tiles
s_axi_dma_adc
axis_inter_adc
S_AXIS0
S00_AXIS
S_AXIS1
S01_AXIS
S_AXIS2
S02_AXIS
S_AXIS3 S03_AXIS
S_AXIS4
S04_AXIS
S_AXIS5 S05_AXIS
S_AXIS6
S06_AXIS
S_AXIS7 S07_AXIS1
S_AXIS8
S08_AXIS2
S_AXIS9 S09_AXIS2
S_AXIS10
S10_AXIS2
S_AXIS11 S11_AXIS2
S_AXIS12
S12_AXIS3
S_AXIS13
S13_AXIS3
S_AXIS14
S14_AXIS3
S_AXIS15
S15_AXIS3
S_AXI_CTRL
S_AXI_CTRL
S00_ARB_REQ_SUPPRESS
S01_ARB_REQ_SUPPRESS
S02_ARB_REQ_SUPPRESS
S03_ARB_REQ_SUPPRESS
S04_ARB_REQ_SUPPRESS
S05_ARB_REQ_SUPPRESS
S06_ARB_REQ_SUPPRESS
S07_ARB_REQ_SUPPRESS
S08_ARB_REQ_SUPPRESS
S09_ARB_REQ_SUPPRESS
S10_ARB_REQ_SUPPRESS
S11_ARB_REQ_SUPPRESS
S12_ARB_REQ_SUPPRESS
S13_ARB_REQ_SUPPRESS
S14_ARB_REQ_SUPPRESS
S15_ARB_REQ_SUPPRESS
AXI4-Stream Interconnect
(Pre-Production)
s00_axi
s_axi_
ps_adc_ddr
UG1433 (v1.2) October 27, 2021
RF Data Converter Evaluation Tool User Guide
tlast_gen_v1_0_0
M00_AXIS
s_axis
m_axis
s00_AXI
tlast_gen_v1_0
(Pre-Production)
axi_dma_0
S_AXI_LITE M_AXI_SG
M_AXI_S2MM
S_AXIS_S2MM
AXI Direct Memory Access)
(Pre-Production)
smartconnect_0
S00_AXI
S01_AXI
AXI SmartConect (Pre-Production)
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Chapter 3: Hardware Design
S_AXI_SG_ADC
ddr4_adc
C0_DDR4_S_AXI dbg_bus[511:0]
M00_AXI
c0_ddr4_ul_clk_sync_rst
DDR4 SDRAM (MIG)
(Pre-Production)
www.xilinx.com
dbg_clk
X23665-012320
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