Xilinx Zynq UltraScale+ RFSoC ZCU208 User Manual page 17

• Write 1 in the corresponding bit of the enable register.
SetTDDRTSEnables 0x0002.
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This controls the hw_trigger_en pins. In this example, it enables the trigger on tile 1.
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• Write 1 in the trigger register.
SetTDDRTSTrig 1.
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This controls the hw_trigger pins.
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UG1433 (v1.2) October 27, 2021
RF Data Converter Evaluation Tool User Guide
Chapter 3: Hardware Design
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